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參數(shù)資料
| 型號： | HMC704LP4E |
| 廠商： | Hittite Microwave Corporation |
| 文件頁數(shù)： | 10/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FRACT-N PLL 16BIT 24QFN |
| 標準包裝： | 1 |
| 類型： | 整數(shù) N/小數(shù) N 分頻 |
| PLL： | 是 |
| 輸入： | CMOS |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.3V，5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VQFN 裸露焊盤 |
| 供應商設備封裝： | 24-QFN 裸露焊盤（4x4） |
| 包裝： | 標準包裝 |
| 其它名稱： | 1127-1066-6 |
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HMC704LP4E
v03.1211
8 GHz fractionaL-n PLL
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
reference input Stage
The reference buffer provides the path from an external reference source (generally crystal based) to the R divider, and
eventually to the phase detector. The buffer has two modes of operation. High Gain (recommended below 200MHz),
and High frequency, for 200 to 350MHz operation. The buffer is internally DC biased, with 100 Ohm internal termina-
tion. For 50 Ohm match, an external 100 Ohm resistance to ground should be added, followed by an AC coupling ca-
pacitance (impedance < 1 Ohm), then to the XREFP pin of the part.
At low frequencies, a relatively square reference is recommended to keep the input slew rate high. At higher frequen-
cies, a square or sinusoid can be used. The following table shows the recommended operating regions for different
reference frequencies. If operating outside these regions the part will normally still operate, but with degraded perfor-
mance.
Minimum pulse width at the reference buffer input is 2.5ns. For best spur performance when R = 1, the pulse width
should be (2.5ns + 8Tps), where Tps is the period of the VCO at the prescaler input. When R > 1 minimum pulse width
is 2.5ns.
table 6. reference Sensitivity table
square Input
sinusoidal Input
Frequency
(MHz)
slew > 0.5V/ns
Recommended swing (Vpp)
Recommended Power Range (dBm)
Recommended
Min
Max
Recommended
Min
Max
< 10
YEs
0.6
2.5
x
10
YEs
0.6
2.5
x
25
YEs
0.6
2.5
ok
8
15
50
YEs
0.6
2.5
YEs
6
15
100
YEs
0.6
2.5
YEs
5
15
150
ok
0.9
2.5
YEs
4
12
200
ok
1.2
2.5
YEs
3
8
200 to 350
x
YEs1
5
10
Note: For greater than 200MHz operation, use buffer in High Frequency Mode. Reg[8] bit 21 = 1
Input referred phase noise of the PLL when operating at 50MHz is between -150 and -156dBc/Hz at 10kHz offset de-
pending upon the mode of operation. The input reference signal should be 10dB better than this floor to avoid deg-
radation of the PLL noise contribution. It should be noted that such low levels are only necessary if the PLL is the domi-
nant noise contributor and these levels are required for the system goals.
Figure 27. Reference Path Input Stage
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HMC704LP4ETR | 制造商:Hittite Microwave Corp 功能描述:IC FRACT-N PLL 16BIT 24QFN |
| HMC705LP4 | 制造商:HITTITE 制造商全稱:Hittite Microwave Corporation 功能描述:6.5 GHz PROGRAMMABLE DIVIDER (N = 1 - 17) |
| HMC705LP4E | 制造商:Hittite Microwave Corp 功能描述:IC DIVIDER HBT PROGR 24-QFN |
| HMC705LP4ETR | 功能描述:IC DIVIDER HBT PROGR 24QFN 制造商:analog devices inc. 系列:- 包裝:剪切帶（CT） 零件狀態(tài):在售 功能:分頻器 頻率:100MHz ~ 6.5GHz RF 類型:- 輔助屬性:- 封裝/外殼:24-VFQFN 裸露焊盤 供應商器件封裝:24-QFN（4x4） 標準包裝:1 |
| hmc706lc3c | 制造商:Hittite Microwave Corp 功能描述:IC CONV NRZ-RZ 13GBPS 16SMD |
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