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參數(shù)資料
| 型號： | HMC704LP4E |
| 廠商： | Hittite Microwave Corporation |
| 文件頁數(shù)： | 21/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FRACT-N PLL 16BIT 24QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 整數(shù) N/小數(shù) N 分頻 |
| PLL： | 是 |
| 輸入： | CMOS |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.3V，5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN 裸露焊盤（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | 1127-1066-6 |
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HMC704LP4E
v03.1211
8 GHz fractionaL-n PLL
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
Proceed as follows:
a. Calculate the GCD of the PD Rate, fpd , and the step size, fstep, GCD( 61.44MHz, 100kHz) = fgcd =
20kHz (same value for all channels)
(same value is used for all channels)
(2000.2MHz/61.44MHz) = 32d =20h (Note: floor = round down to nearest integer).
d. Calculate the equivalent integer boundary frequency, fint = Nint*fpd = 1966.080MHz.
e. Calculate the fractional register setting for the channel, “Reg 04h” = Nfrac = 224(fvco-fint)/fpd =
ceiling(224*(2000.2-1966.08)/61.44) = 9317035d=8E2AABh. It is important that this parameter be
rounded up (hence the ‘ceiling’ function).
The fractional value is programmed for each new channel. The integer value is only programmed initially and then only
if the output crosses an integer boundary.
Seed register and autoSeed Mode
The start phase of the fractional modulator digital phase accumulator (DPA) may be set to one of four pos-
sible default values via the seed register “Reg 06h”[1:0]. If autoseed “Reg 06h”[8] is set, then the PLL will automatically
reload the start phase from “Reg 06h”[1:0] into the DPA every time a new fractional frequency is selected. If autoseed is
not set, then the PLL will start new fractional frequencies with the value left in the DPA from the last frequency. Hence
the start phase will effectively be random. Certain zero or binary seed values may cause spurious energy correlation at
specific frequencies. Correlated spurs are advantageous only in very special cases where the spurious are known to
be far out of band and are removed in the loop filter. For most cases a pseudo-random seed setting (“Reg 06h”[1:0] =2
or 3) is recommended. Further, since the autoseed always starts the accumulators at the same place, performance is
repeatable if autoseed is used. “Reg 06h”[1:0]=2 is recommended.
Power on reset
The HMC704LP4E features a hardware Power on Reset (POR) on the digital supply DVDD. All chip registers will be
reset to default states approximately 250us after power up of DVDD. Once the supply is fully up, if the power supply
then drops below 0.5V the digital portion will reset.
Power Down Mode
Hardware Power Down
Chip enable may be controlled from the hardware CEN pin 23, or it may be controlled from the serial port. “Reg 01h”[0]
=1 assigns control to the CEN pin. “Reg 01h”[0] =0 assigns control to the serial port “Reg 01h”[1]. For hardware test
reasons or some special applications it is possible to force certain blocks to remain on inside the chip , even if the chip
is disabled. see the register “Reg 01h” description for more details.
chip identification
Version information may be read from the PLL by reading the content of chip_ID in “Reg 00h”.
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