8 GHz fractionaL-n PLL For price, deli" />
參數(shù)資料
型號(hào)： HMC704LP4E
廠商： Hittite Microwave Corporation
文件頁(yè)數(shù)： 32/44頁(yè)
文件大?。?/td> 0K
描述： IC FRACT-N PLL 16BIT 24QFN
標(biāo)準(zhǔn)包裝： 1
類型： 整數(shù) N/小數(shù) N 分頻
PLL： 是
輸入： CMOS
輸出： CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/無(wú)
頻率 - 最大： 8GHz
除法器/乘法器： 是/無(wú)
電源電壓： 3.3V，5V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-VQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 24-QFN 裸露焊盤（4x4）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 1127-1066-6
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HMC704LP4E
v03.1211
8 GHz fractionaL-n PLL
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
table 19. reg 06h SD cfG register
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
[1:0]
R/W
seed select
2
selects the seed in Fractional Mode
00: 0 seed
01: lsb seed
02: B29D08h seed
03: 50F1CDh seed
Note; Writes to this register are stored in the PLL and are only
loaded into the modulator when a frequency change is executed
and if autoseed Reg06h[13] =1
[3:2]
R/W
Modulator order
2
select the Delta sigma Modulator Type
0: Reserved
1: Reserved
2: Mode B Offers better out of band spectral performance. Mode B
Required for Exact Frequency Mode.
3: Mode A Offers better in band spectral performance
[6:4]
R/W
Reserved
3
7
[7]
R/W
frac_bypass
1
0
0: Use Modulator, Required for Fractional Mode,
1: Bypass Modulator, Required for Integer Mode
Note: In bypass fractional modulator output is ignored, but frac-
tional modulator continues to be clocked if frac_rstb =1, Can be
used to test the isolation of the digital fractional modulator from the
VCO output in integer mode
[8]
R/W
autoseed
1
1: loads the modulator seed (start phase) whenever the frac regis-
ter is written
0: when frac register write changes frequency, modulator starts
with previous contents
[9]
R/W
clkrq_refdiv_sel
1
selects the modulator core clock source- for Test Only
1: VCO divider clock
0: Ref divider clock
Ignored if bits [10] or [21] are set
[10]
R/W
Modulator Core Clk select
1
0
0 - Modulator auxclk, 1- Modulator VCO Clock delay
[11]
R/W
frac_rstb
1
0: disable Modulator, use for Integer Mode or Integer Mode with
CsP
1: Enable Modulator Core, required for Fractional Mode, or Integer
isolation testing
[12]
R/W
Reserved
1
0
[13]
R/W
Reserved
1
0
[15:14]
R/W
Reserved
2
0
Reserved
[17:16]
R/W
Reserved
2
0
Program to 3 decimal “11” binary
[18]
R/W
BIsT Enable
1
0
Enable Built in self Test
[20:19]
R/W
RDIV BIsT Cycles
2
0
0:1023
1:2047
2:3071
3:4095
[21]
R/W
Reserved
1
0
Reserved
[22]
R/W
Reserved
1
0
Reserved
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