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參數(shù)資料
| 型號： | HDMP-1032 |
| 英文描述： | 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器) |
| 中文描述： | 1.4 GBd發(fā)射機(jī)芯片組與CIMT編碼器/解碼器和可變數(shù)據(jù)速率（帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd傳送器） |
| 文件頁數(shù)： | 8/32頁 |
| 文件大小： | 346K |
| 代理商： | HDMP-1032 |
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8
of the REFCLK. By adjusting the
phase of the data word rather
than REFCLK, the optimal setup
time is achieved for the input
latches of the chip interfacing to
the Rx.
As the relative phase between the
HSIN
±
input and the REFCLK
drift slowly over time due to envi-
ronmental variations, the PASS
system is able to absorb this to
some degree, and is able to reset
and re-optimize the sampling
when the margin is exceeded.
DELAY Block
The parallel DELAY block has an
adjustable delay range of 20% to
80% of the data word. Its delay
is controlled by the SYNC LOGIC
block. This delay block is used
for all of the data bits, flag bit,
as well as the status bits.
OUTPUT LATCH Block
This block is a bank of positive
edge triggered D-flip/flops. The
clock is selected by the SYNC
LOGIC block to be either the re-
covered clock RXCLK1 when the
PASS system is disabled, or the
REFCLK when the PASS system
is enabled (PASSENB=1).
SYNC LOGIC Block
The SYNC LOGIC block’s func-
tion is to compare the phase of
the recovered data to REFCLK, to
set the state of the DELAY block,
to detect when the DELAY range
has been exceeded, and to re-
cover with a new DELAY setting.
It is also designed to support a
master/slave configuration in a
multi-channel environment.
When RXREADY goes high, the
optimal delay choice is deter-
mined at the shift output
SHFOUT:
SHFOUT = 0 DELAY retract
SHFOUT = 1 DELAY extend
The actual setting of the DELAY
block is determined with the shift
input SHFIN.
When the phase of the REFCLK
drifts to within 10% of the word
boundary, the RXDSLIP output
is set high, and a new choice of
SHFOUT is chosen. The shift re-
quest output SQROUT is set high
when a RXDSLIP condition is
detected, or if the shift request
input SRQIN goes high.
Figure 4.2. Single channel configuration with PASS enabled (PASSENB=1).
Recovered data words and RXCLK0/1 are synchronous with REFCLK.
HSOUT±
HSIN±
Rx
Tx
TXCLK
REFCLK
REFCLK
SRQOUT
NC
SRQIN
SHFIN
SHFOUT
RXCLK0/1
RX[0-15]
DATA 16 BITS
TX[0-15]
PASSENB
+V
CC
Single Channel Configuration
In a single channel configuration,
SHFIN is simply tied to SHFOUT
as shown in Figure 4.2. The daisy
chaining signal SRQIN is set low
(grounded) and SRQOUT is left
unconnected.
After RXREADY goes high, the
DELAY block can absorb a phase
variation between the serial input
HSIN
±
and the REFCLK a mini-
mum of ideally
±
4 serial bits,
or 20% of the word period. This
margin is reduced due to finite
rise/fall times and setup times
of the internal circuitry.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1032A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034A | 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
| HDMP-1512 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
| HDMP-1514 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
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