- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370499 > HDMP-1032 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器) PDF資料下載
參數(shù)資料
| 型號(hào)： | HDMP-1032 |
| 英文描述： | 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器) |
| 中文描述： | 1.4 GBd發(fā)射機(jī)芯片組與CIMT編碼器/解碼器和可變數(shù)據(jù)速率（帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd傳送器） |
| 文件頁數(shù)： | 26/32頁 |
| 文件大?。?/td> | 346K |
| 代理商： | HDMP-1032 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁
26
Integrator Capacitor and Supply
Bypassing/Grounding
Figure 12 shows the PLL inte-
grator capacitors, power supply
capacitors and required ground-
ing for the Tx and Rx chips.
Integrator Capacitor
An integrator capacitor (C2) is
required by both the Tx and Rx
for them to function properly.
This cap is used by the PLL for
frequency and phase lock, and di-
rectly sets the stability and lockup
times. A 0.1
μ
F capacitor is recom-
mended for each DIV1/0 setting.
Supply Bypassing/Grounding
The HDMP-1032/34 chipset has
been tested to work well with a
single power plane, assuming that
it is a fairly clean power plane. As
a result, all of the separate power
supplies (V
CC
, V
CC
_TTL, and
V
CC
_HS) can be connected onto
this plane. The bypassing of V
CC
to ground should be done with a
0.1
μ
F capacitor (C1).
TTL and HighSpeed
I/O I-TTL and O-TTL
These I/O pins are TTL compatible.
A simplified schematic diagram of
the I/O cells is shown in Figure 13.
High-Speed Interface: HS_IN and
HS_OUT
The simplified schematic diagrams
of HS_IN and HS_OUT are shown
in Figure 14. The HS_IN input cell
is implemented with internal 50
resistors between the differential
input lines HSIN
±
to GND_HS.
The HSIN
±
inputs have internal
bias provided and the signals are
AC coupled in with 0.1
μ
F capaci-
tors. It is recommended that
differential signals be applied
across the HSIN
±
inputs (Figure
15a), although a single-ended
connection is acceptable. In this
case, the unused input must be
terminated with 50
AC coupled
to ground.
The HS_OUT output cell is
designed to deliver PECL swings
directly into 50
. The output
impedance is matched to 50
and
has a VSWR of less than 2:1 to
above 2 GHz. This output is
ideal for driving the HS_IN input
through a 50
cable and a
0.1
μ
F coupling capacitor. The
HS_OUT driver can also be
Figure 12. HDMP-1032 (Tx) and HDMP-1034 (Rx) Power Supply Pins.
C1
C1 = BYPASS CAPACITOR
C2 = PLL INTEGRATOR CAPACITOR
0.1 μF
0.1 μF
V
CC
_A1
HDMP-1032
Tx
C1
C1
C1
C1
C2
C1
C1
C1
C1
V
CC
_A2
C1
NOTE: V
_A PINS SUPPLY VOLTAGE SHOULD
COME FROM A LOW NOISE SOURCE.
V
CC
_A
HDMP-1034
Rx
C1
C1
C2
C1
C1
C1
C1
C1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HDMP-1034 | 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器) |
| HDMP-1512 | Fibre Channel Transmitter Chipset(光纖通道傳送芯片) |
| HDMP-1514 | Fibre Channel Receiver Chipset(光纖通道接收芯片) |
| HDMP-1526 | Transistor Diode Kit;Contents Of Kit:Transistor/Diode Kit |
| HDMP-1536 | Fibre Channel Transceiver Chip |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1032A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034A | 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
| HDMP-1512 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
| HDMP-1514 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。