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參數(shù)資料
| 型號： | HDMP-1032 |
| 英文描述： | 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器) |
| 中文描述： | 1.4 GBd發(fā)射機芯片組與CIMT編碼器/解碼器和可變數(shù)據(jù)速率（帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd傳送器） |
| 文件頁數(shù)： | 24/32頁 |
| 文件大?。?/td> | 346K |
| 代理商： | HDMP-1032 |
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24
Tx Operation Principles
The HDMP-1032 (Tx) is imple-
mented monolithically in a high
performance 25 GHz f
t
silicon
bipolar process. The Tx performs
the following functions for link
operation:
Latching Parallel Word Input
Phase Lock to TXCLK
High-Speed Clock
Multiplication
Word Encoding
Parallel to Serial Multiplexing
In normal operation, the Tx
phase locks to a user supplied
word rate clock and multiplies
the frequency to produce
the high-speed serial clock.
The Tx can accept either 16 or
17 bit wide parallel data and
produce a 20 bit encoded word.
Similarly, 14 bit control words
can be transmitted in a 20 bit
encoded word.
Tx Encoding
A simplified block diagram of the
transmitter is shown in Figure 3.
The PLL/Clock Generator locks
onto the incoming word rate
clock and multiplies it up to the
serial clock rate. It also generates
all the internal clock signals
required by the Tx chip.
The data inputs, TX[0-15],
as well as the control signals;
TXDATA, TXCNTL and TXFLAG
are latched in on the rising edge
of an internally generated word
rate clock. The word field is then
encoded depending on the state
of the TXDATA and TXCNTL
signals. At the same time, the
coding field is generated. At this
point, the entire word has been
constructed in parallel form and
its sign is determined. This word
sign is compared with the accu-
mulated sign of previously trans-
mitted bits to decide whether to
invert the word. If the sign of the
current word is the same as the
sign of the previously transmitted
bits, then the word is inverted. If
the signs are opposite, the word
is not inverted. No inversion is
performed if the word is an idle
word.
The Word Field and Coding
Field are encoded depending on
TXDATA, TXCNTL, TXFLAG,
TXFLGENB as well as two inter-
nally generated signals, O/E and
ACCMSB.
When TXFLGENB is high
and ESMPXENB is low, O/E is
equivalent to TXFLAG. This
is equivalent to adding an addi-
tional bit to the data field. When
TXFLGENB is also low, O/E
alternates between high and low
for data words. This allows the
link to perform more extensive
error detection when the extra
bit is unused.
ACCMSB is the sign of the previ-
ously transmitted data. This is
used to determine which type
of Idle Word should be sent.
When ACCMSB is low, IW1a is
sent and when ACCMSB is high,
IW1b is sent. This effectively
drives the accumulated offset of
transmitted bits back toward the
balanced state.
Tx Phase-Lock Loop
The block diagram of the trans-
mitter phase-lock loop (PLL) is
shown in Figure 10. It consists
of a sequential frequency detector,
loop filter, VCO, clock generation
circuitry and a lock indicator.
The outputs of the frequency
detector pass through a charge
pump filter that controls the
center frequency of the VCO.
Figure 10. HDMP-1032 (Tx) Phase-Lock Loop.
FREQUENCY
DETECTOR
TXCLK
CLOCK
GENERATOR
LOCK
DETECT
DIVIDE BY N
LOOP
FILTER
VCO
TSTCLKEN
TXCLK
1
0
TXDIV1/0
INTERNAL CLOCKS
EXTERNAL CAP
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PDF描述 |
|---|---|
| HDMP-1034 | 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器) |
| HDMP-1512 | Fibre Channel Transmitter Chipset(光纖通道傳送芯片) |
| HDMP-1514 | Fibre Channel Receiver Chipset(光纖通道接收芯片) |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1032A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034A | 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
| HDMP-1512 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
| HDMP-1514 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
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