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參數(shù)資料
| 型號(hào)： | HDMP-1032 |
| 英文描述： | 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器) |
| 中文描述： | 1.4 GBd發(fā)射機(jī)芯片組與CIMT編碼器/解碼器和可變數(shù)據(jù)速率（帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd傳送器） |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 346K |
| 代理商： | HDMP-1032 |
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16
HDMP-1032 (Tx) Pin Definition
User Mode Options
Name
TXFLGENB
Pin
10
Type
I-TTL
Signal
Flag Bit Mode Select:
When this input is high, the TXFLAG bit
input is sent as an extra 17th data bit during data word transfers.
As an example, the flag bit can be used as an even or odd word
indicator for 32 bit transmission. The RXFLGENB input on the Rx
chip must be set to the same value as the TXFLGENB pin.
Enhanced Simplex Mode Enable:
Enables scrambling of the Flag
Bit encoding. The ESMPXENB pin on the Rx chip must be set to
the same value. This mode should be enabled unless compatibility
with previous versions of G-Link (i.e. HDMP-1024/1014) is desired
desired which don’t have this feature.
Transmit Data Word:
This input tells the chip that the user has
valid data to be transmitted. When this pin is asserted and
TXCNTL is low, bits TX[0-15] and optionally TXFLAG are encoded
and sent as a data word.
Transmit Control Word:
This input tells the Tx chip that the user
is requesting a control word to be transmitted. When this pin is
asserted, bits TX[0-13] are sent as a control word. If TXCNTL and
TXDATA are asserted simultaneously, TXCNTL takes precedence.
Idle words are transmitted if both TXDATA and TXCNTL are low.
ESMPXENB
11
I-TTL
TXDATA
5
I-TTL
TXCNTL
4
I-TTL
High-Speed Serial/Parallel I/O
HSOUT+
HSOUT-
TX[0]
TX[1]
TX[2]
TX[3]
TX[4]
TX[5]
TX[6]
TX[7]
TX[8]
TX[9]
TX[10]
TX[11]
TX[12]
TX[13]
TX[14]
TX[15]
TXFLAG
20
19
46
47
50
51
52
53
54
55
58
59
60
61
62
63
2
3
6
HS_OUT
Serial Data Output:
These pins form a buffer line logic driver,
which is a 50
terminated PECL compatible output.
Word Inputs:
When sending data words, TX[0-15] are serialized.
When sending control words, TX[0-13] are serialized.
I-TTL
I-TTL
Flag Bit:
When TXFLGENB is active, this input is sent as an extra
data bit in addition to the 16 data word bits. When TXFLGENB is
not asserted, this input is ignored and an alternating internal flag
bit is transmitted to allow the Rx chip to perform error detection
during data word transfers. The Flag Bit is not sent when a control
word is transmitted.
相關(guān)PDF資料 |
PDF描述 |
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| HDMP-1034 | 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器) |
| HDMP-1512 | Fibre Channel Transmitter Chipset(光纖通道傳送芯片) |
| HDMP-1514 | Fibre Channel Receiver Chipset(光纖通道接收芯片) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1032A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034A | 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
| HDMP-1512 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
| HDMP-1514 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
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