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參數(shù)資料
| 型號： | HDMP-1032 |
| 英文描述： | 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器) |
| 中文描述： | 1.4 GBd發(fā)射機芯片組與CIMT編碼器/解碼器和可變數(shù)據(jù)速率（帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd傳送器） |
| 文件頁數(shù)： | 27/32頁 |
| 文件大小： | 346K |
| 代理商： | HDMP-1032 |
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connected directly into a high-
speed 50
oscilloscope. For opti-
mum performance, both outputs
should see the same impedance.
It is necessary that all HS_OUT
outputs be terminated into 50
.
Figure 15 shows various methods
of interfacing HS_OUT to HS_IN
and standard PECL logic.
Data Bus Line/Broadcast
Transmission
The GND_HS pins are normally
tied to ground to provide 50
in-
put impedance. For 1:N broadcast
applications, 18K
series resistors
can be inserted between GND_HS
and -5V to provide
an effective high impedance as
shown in Figure 16. A Port-
Bypass Circuit (PBC) can also be
used in a broadcast application as
shown in Figure 17. Each
input and output PBC is a dedi-
cated channel and impedance
matched to the transmission
line. This is a superior method of
achieving a broadcast mode com-
pared to Figure 16, but does add
an additional IC. More receivers
can be added by cascading PBC
ICs or using a PBC with more ports.
Figure 13. O-TTL and I-TTL Simplified Circuit Schematic.
V
CC
_TTL
O_TTL
I_TTL
V
CC
GND
1.4 V
GND_TTL
GND
V
CC
ESD
PROTECTION
ESD
PROTECTION
Figure 14. HS_OUT and HS_IN Simplified Circuit Schematic.
50
V
CC
HS_IN
0.1
μ
F
GND
GND
V
CC
50
ZO = 50
HS_OUT
GND_HS
ESD
PROTECTION
ESD
PROTECTION
0.1
μ
F
相關(guān)PDF資料 |
PDF描述 |
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| HDMP-1034 | 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器) |
| HDMP-1512 | Fibre Channel Transmitter Chipset(光纖通道傳送芯片) |
| HDMP-1514 | Fibre Channel Receiver Chipset(光纖通道接收芯片) |
| HDMP-1526 | Transistor Diode Kit;Contents Of Kit:Transistor/Diode Kit |
| HDMP-1536 | Fibre Channel Transceiver Chip |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1032A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034A | 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
| HDMP-1512 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
| HDMP-1514 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
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