參數(shù)資料
型號： HDMP-1032
英文描述： 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器)
中文描述： 1.4 GBd發(fā)射機芯片組與CIMT編碼器/解碼器和可變數(shù)據(jù)速率（帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd傳送器）
文件頁數(shù)： 2/32頁
文件大?。?/td> 346K
代理商： HDMP-1032
2
REFCLK. This feature is particu-
larly useful when the Tx clock
and REFCLK are synchronous.
The PASS system also supports
synchronization of multiple
channels.
The chipset is compatible with
previous versions of the G-Link
chipset (HDMP-10x2/10x4) pro-
vided the latter are used in 16 bit
Simplex with Periodic Sync Pulse
or External Reference Oscillator
Mode (Simplex Method II or III).
Table of Contents
Topic
Page
Typical Applications ................................................................................................... 3
Setting the Operating Data Rate Range.................................................................. 4
Transmitter Block Diagram ....................................................................................... 5
Receiver Block Diagram ............................................................................................ 6
Parallel Automatic Synchronization System.......................................................... 7
Transmitter Timing.................................................................................................... 10
Receiver Timing...........................................................................................................11
DC Electrical Specifications .....................................................................................12
AC Electrical Specifications .....................................................................................12
TXCLK and REFCLK Requirements ........................................................................... 13
Absolute Maximum Ratings ......................................................................................13
Thermal Characteristics ............................................................................................14
I/O Type Definitions .................................................................................................... 14
Pin-Out Diagrams ........................................................................................................15
Transmitter Pin Definitions........................................................................................16
Receiver Pin Definitions ............................................................................................18
Mechanical Dimensions ............................................................................................21
Appendix: Internal Architecture Information
Line Code Description ................................................................................................22
Data, Control, and Idle Word Codes ........................................................................22
Tx Operation Principles – Encoding & Phase Lock Loop .................................... 24
Rx Operation Principles – Decoding & Phase Lock Loop.................................... 25
Integrator Capacitor & Power Supply
Bypassing/Grounding.................................................................................................26
TTL and High Speed I/O ............................................................................................. 26
Data Bus Line/Broadcast Transmission .................................................................27
Nomenclature Changes between
HDMP-1032/34 and HDMP-1022/24..........................................................................30
Pin Cross Reference Table........................................................................................31
相關(guān)PDF資料
PDF描述
HDMP-1034 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器)
HDMP-1512 Fibre Channel Transmitter Chipset(光纖通道傳送芯片)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HDMP-1032A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate
HDMP-1034 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate
HDMP-1034A 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set
HDMP-1512 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset
HDMP-1514 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset
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