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參數(shù)資料
| 型號： | HDMP-1032 |
| 英文描述： | 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器) |
| 中文描述： | 1.4 GBd發(fā)射機芯片組與CIMT編碼器/解碼器和可變數(shù)據(jù)速率（帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd傳送器） |
| 文件頁數(shù)： | 17/32頁 |
| 文件大小： | 346K |
| 代理商： | HDMP-1032 |
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17
HDMP-1032 (Tx) Pin Definition (continued)
PLL/Clock Generator
Name
Pin
TXCAP0
32
TXCAP1
33
Type
C
Signal
Loop Filter Capacitor:
A 0.1
μ
F min. loop filter capacitor, C2, must
be connected across TXCAP0 and TXCAP1 for all combinations of
TXDIV1/TXDIV0. See Figure 12.
Transmit Word Clock Input:
When TCLKENB is low, this word rate
clock input is phase locked and multiplied to generate the high-
speed serial clock. When TCLKENB is high, the PLL is bypassed
and TXCLK becomes the serial clock.
VCO Divider Select:
These pins program the VCO divider chain to
operate at full, half or quarter speed. See Typical Operating Rates
table and Figure 2.
Locked to TXCLK:
This pin goes high when the transmit PLL
achieves frequency lock to the TXCLK signal.
TXCLK
37
I-TTL
TXDIV0
TXDIV1
26
27
I-TTL
LOCKED
12
O-TTL
Power Supply/Ground
V
CC
13
24
36
49
64
8
41
17
S
Logic Power Supply:
Normally 3.3 volts. This power supply is
used for the internal transmitter logic.
V
CC
_TTL
S
TTL Power Supply:
Normally 3.3 volts. Used for all TTL transmitter
input and output buffer cells.
Serial Output Power Supply:
Normally 3.3 volts. Used for Serial
Output pins.
Analog Power Supply:
Normally 3.3 volts. Used for the analog
section.
Ground:
Normally 0 volts. Tie to ground.
V
CC
_HS
S
V
CC
_A1
V
CC
_A2
GND
31
57
1
14
25
35
48
9
40
18
30
56
S
S
GND_TTL
S
TTL Ground:
Normally 0 volts. Tie to ground.
GND_HS
GND_A1
GND_A2
Test Mode/No Connect Pins
TCLKENB
S
S
Serial Output Ground:
Normally 0 volts.
Analog Ground:
Normally 0 volts.
28
I-TTL
Enable External Serial Rate Clock Input:
When set high, this input
causes the TXCLK input to be used for the serial transmit clock
rather than the internal VCO clock. It is intended for diagnostic
purposes and normally tied low.
No Connect:
These pins should be left unconnected.
NC
7
15
16
21
22
23
29
34
38
39
42
43
44
45
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| HDMP-1034 | 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器) |
| HDMP-1512 | Fibre Channel Transmitter Chipset(光纖通道傳送芯片) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1032A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034A | 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
| HDMP-1512 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
| HDMP-1514 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
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