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參數(shù)資料
| 型號： | HDMP-1032 |
| 英文描述： | 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器) |
| 中文描述： | 1.4 GBd發(fā)射機(jī)芯片組與CIMT編碼器/解碼器和可變數(shù)據(jù)速率（帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd傳送器） |
| 文件頁數(shù)： | 5/32頁 |
| 文件大?。?/td> | 346K |
| 代理商： | HDMP-1032 |
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5
Figure 3. HDMP-1032 Transmitter Block Diagram.
The C-Field logic, based on the
inputs at TXCNTL, TXDATA,
TXFLGENB and TXFLAG, sup-
plies the four bits of the C-field
to the encoded word mux. These
bits contain information regard-
ing the word type: Control, Data
or Idle. In order for the TXFLAG
bit to be used as an additional
data bit, TXFLGENB must be set
high on the Tx and RXFLGENB
must be set high on the Rx. If
scrambling of the encoding of the
flag bit is desired, ESMPXENB pin
must be set high on both the Tx
and Rx. See Flag Descrambler
section on next page for a more
detailed description of the
enhanced simplex mode.
The W-Field logic (word field)
presents either bits TX[0-15]
or an Idle Word to the encoded
word mux.
Encoded Word Mux
The Word Mux accepts the four
encoding bits from the C-Field
and 16 data bits from the
W-Field. These 20 bits of parallel
information are then multiplexed
to a serial line based on the
internal high-speed serial clock.
HDMP-1032 Tx Block Diagram
The HDMP-1032 transmitter was
designed to accept 16 bit wide
parallel words and transmit them
over a high-speed serial line. The
HDMP-1032 performs the follow-
ing functions:
Latching parallel word input
Phase lock to TXCLK
High speed clock multiplication
Word encoding
Parallel to Serial Multiplexing
PLL/Clock Generator
The Phase Lock Loop and Clock
Generator are responsible for
generating all the internal clocks
needed by the transmitter to
perform its functions. These
clocks are based on a supplied
word clock (TXCLK) and control
signals (TXDIV1/0, TCLKENB).
TXCLK is the incoming word
clock. The PLL/Clock Generator
locks on to this incoming
rate and multiplies the word
rate clock by 20 (16 word bits
+ 4 encoding bits). As lock is
achieved, LOCKED is set high.
The TXDIV1/0 pins configure the
transmitter to accept incoming
data words within the desired
frequency range.
By setting TCLKENB high, the
user may provide an external
TTL high speed serial clock at
TXCLK. This clock replaces the
internal VCO clock and is in-
tended for diagnostic purposes
only. This uncharacterized signal
is used directly by the high-speed
serial circuitry to output the se-
rial data at speeds that are not
within the VCO range.
C-Field and W-Field
Encoder Logic
This logic determines what infor-
mation is sent to the encoded
word mux. If TXCNTL is high, the
logic sends bits TX[0-13] and a
C-Field (coding field) encoded
as a control word regardless of
the state of TXDATA. If TXCNTL
is low and TXDATA is high,
the logic sends TX[0-15] and a
C-Field encoded as a data word.
If neither TXCNTL nor TXDATA
is set high, then the transmitter
assumes the link is not being
used. In this case, the logic sub-
mits an Idle Word to the encoded
word mux to maintain the DC
balance on the serial link and
allow the receiver to maintain
frequency and phase lock.
C-FIELD
ENCODER
TXFLAG
TX[0-15]
W-FIELD
ENCODER
INVERT
WORD
MUX
T
E
T
T
T
L
PLL / CLOCK
GENERATOR
A
TXCAP0
TXCAP1
HSOUT
FLAG
ENCODER
TXDATA
TXCNTL
L
I
I
L
SIGN
+
相關(guān)PDF資料 |
PDF描述 |
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| HDMP-1034 | 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器) |
| HDMP-1512 | Fibre Channel Transmitter Chipset(光纖通道傳送芯片) |
| HDMP-1514 | Fibre Channel Receiver Chipset(光纖通道接收芯片) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1032A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034A | 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
| HDMP-1512 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
| HDMP-1514 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
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