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參數(shù)資料
| 型號： | GM72V66841Exx |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 2097152字× 8位× 4個銀行同步動態(tài)RAM |
| 文件頁數(shù)： | 31/57頁 |
| 文件大?。?/td> | 592K |
| 代理商： | GM72V66841EXX |
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LG Semicon
GM72V66841CT/CLT
2.
Same bank, different ROW address:
When
the ROW address changes, consecutive write
commands cannot be executed; it is necessary to
separate the two write commands with a
Precharge command and a bank-active command.
3. Different bank:
When the bank changes, the
write command can be performed after an
interval of no less than 1 cycle, provided that the
other bank is in the bank-active state. However,
in the case of a burst write, data will continue to
be written until one cycle before the read
command is executed(as in the case of the same
bank and the same address).
Read command to Precharge interval (same
bank):
When the Precharge command is
executed for the same bank as the read command
that preceded it, the minimum interval between
the two commands is one cycle. However, since
the output buffer then becomes High-Z after the
cycles defined by l
HZP
, there is a possibility that
burst read data output will be interrupted, if the
Precharge command is input during burst read.
To read all data by burst read, the cycles defined
by l
EP
must be assured as an interval from the
final data output to Precharge command
execution.
READ to Precharge Command Interval (same bank) : To output all data
CLK
Command
Dout
READ
out A0
l
EP
= -
1 Cycle
CL=2
PRE/PALL
out A1
out A2
out A3
CAS Latency = 2, Burst Length = 4
30
CLK
Command
Dout
READ
out A0
l
EP
= -
2 Cycle
CL=3
PRE/PALL
out A1
out A2
out A3
CAS Latency = 3, Burst Length = 4
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