參數(shù)資料
型號： DS3106LN+
廠商： Maxim Integrated Products
文件頁數(shù)： 9/92頁
文件大小： 0K
描述： IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 160
類型： 定時卡 IC，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum，電信
輸入： CMOS，TTL
輸出： CMOS，LVDS，LVPECL，TTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 無/是
頻率 - 最大： 312.5MHz
電源電壓： 1.62 V ~ 1.98 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
產(chǎn)品目錄頁面： 1429 (CN2011-ZH PDF)
DS3106
17
gradually decays in the absence of events. When events occur infrequently, the accumulator value decays fully
between events and no alarm is declared. When events occur close enough together, the accumulator increments
faster than it can decay and eventually reaches the alarm threshold. After an alarm has been declared, if events
occur infrequently enough, the accumulator can decay faster than it is incremented and eventually reaches the
alarm clear threshold. The leaky bucket events come from the frequency range and fast activity monitors.
There is one leaky bucket configuration common to both inputs that has programmable size, alarm declare
threshold, alarm clear threshold, and decay rate, all of which are specified in the LB0x registers.
Activity monitoring is divided into 128ms intervals. The accumulator is incremented once for each 128ms interval in
which the input clock is inactive for more than two cycles (more than four cycles for 125MHz, 62.5MHz, 25MHz,
and 10MHz input clocks). Thus, the “fill” rate of the bucket is at most 1 unit per 128ms, or approximately 8
units/second. During each period of 1, 2, 4, or 8 intervals (programmable), the accumulator decrements if no
irregularities occur. Thus, the “l(fā)eak” rate of the bucket is approximately 8, 4, 2, or 1 units/second. A leak is
prevented when a fill event occurs in the same interval.
When the value of an accumulator reaches the alarm threshold (LB0U register), the corresponding ACT alarm bit is
set to 1 in the ISR2 register, and the clock is marked invalid in the VALSR1 register. When the value of an
accumulator reaches the alarm clear threshold (LB0L register), the activity alarm is cleared by clearing the clock’s
ACT bit. The accumulator cannot increment past the size of the bucket specified in the LB0S register. The decay
rate of the accumulator is specified in the LB0D register. The values stored in the leaky bucket configuration
registers must have the following relationship at all times: LB0S
When the leaky bucket is empty, the minimum time to declare an activity alarm in seconds is LB0U / 8. The
minimum time to clear an activity alarm in seconds is 2^LB0D
× (LB0S – LB0L) / 8. As an example, assume LB0U
= 8, LB0L = 1, LB0S = 10, and LB0D = 0. The minimum time to declare an activity alarm would be 8 / 8 = 1 second.
The minimum time to clear the activity alarm would be 2^0
× (10 – 1) / 8 = 1.125 seconds.
7.5.3 Selected Reference Activity Monitoring
The input clock that T0 DPLL is currently locked to is called the selected reference. The quality of a DPLL’s
selected reference is exceedingly important, since missing cycles and other anomalies on the selected reference
can cause unwanted jitter, wander, or frequency offset on the output clocks. When anomalies occur on the selected
reference, they must be detected as soon as possible to give the DPLL opportunity to temporarily disconnect from
the reference until the reference is available again. By design, the regular input clock activity monitor (Section
7.5.2) is too slow to be suitable for monitoring the selected reference. Instead, each DPLL has its own fast activity
monitor that detects that the frequency is within range (approximately 10,000ppm) and detects inactivity within
approximately two missing reference clock cycles (approximately four missing cycles for 125MHz, 62.5MHz,
25MHz, and 10MHz references).
When the T0 DPLL detects a no-activity event, it immediately enters mini-holdover mode to isolate itself from the
selected reference and sets the SRFAIL latched status bit in MSR2. The setting of the SRFAIL bit can cause an
interrupt request if the corresponding enable bit is set in IER2. If MCR10:SRFPIN = 1, the SRFAIL output pin
follows the state of the SRFAIL status bit. When PHLIM1:NALOL = 0 (default), the T0 DPLL does not declare loss-
of-lock during no-activity events. If the selected reference becomes available again before any alarms are declared
by the activity monitor, the T0 DPLL continues to track the selected reference using nearest edge locking (
±180°)
to avoid cycle slips. When NALOL = 1, the T0 DPLL declares loss-of-lock during no-activity events. This causes the
T0 DPLL state machine to transition to the loss-of-lock state, which sets the MSR2:STATE bit and causes an
interrupt request if enabled. If the selected reference becomes available again before any alarms are declared by
the activity monitor, the T0 DPLL tracks the selected reference using phase/frequency locking (
±360°) until phase
lock is reestablished.
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