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參數(shù)資料
| 型號： | DS3106LN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/92頁 |
| 文件大小： | 0K |
| 描述： | IC TIMING LINE CARD 64-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類型： | 定時(shí)卡 IC，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum，電信 |
| 輸入： | CMOS，TTL |
| 輸出： | CMOS，LVDS，LVPECL，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 312.5MHz |
| 電源電壓： | 1.62 V ~ 1.98 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 1429 (CN2011-ZH PDF) |
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DS3106
14
7. Functional Description
7.1
Overview
The DS3106 has two input clocks, two output clocks, and a high-performance DPLL known as T0. Figure 3-1. The
two input clocks are CMOS/TTL (5V tolerant) and can accept signals from 2kHz to 125MHz. Each input clock is
monitored continually for activity. SRFAIL is set or cleared based on the activity of the selected input.
The T0 DPLL can directly lock to many common datacom and telecom frequencies, including, but not limited to,
8kHz, DS1, E1, 10MHz, 19.44MHz, and 38.88MHz, as well as Ethernet frequencies including 25MHz, 62.5MHz,
and 125MHz. The DPLL can also lock to multiples of the standard direct-lock frequencies including 8kHz. The T0
DPLL has all the features needed for synchronizing a line card to dual redundant system timing cards.
The T0 DPLL includes these features:
A full state machine for automatic transitions among free-run, locked, and holdover states
Adjustable PLL characteristics, including bandwidth, pull-in range, and damping factor
Six bandwidth selections from 18Hz to 400Hz
Frequency conversion between input and output using digital frequency synthesis
Combined performance of a stable, consistent digital PLL and low-jitter analog output PLLs
Ability to lock to several common telecom and Ethernet frequencies plus multiples of the standard direct lock
frequencies including 8kHz
Instant digital one-second averaging and free-run holdover modes
Typically, the internal state machine controls the T0 DPLL, but manual control by system software is also available.
The outputs of the T0 DPLL can be connected to seven output DFS engines. See Figure 7-1. Three of these output
DFS engines are associated with high-speed APLLs that multiply the DPLL clock rate and filter DPLL output jitter.
The outputs of the APLLs are divided down to make a wide variety of possible frequencies available at the output
clock pins.
The OC3 and OC6 output clocks can be configured for a variety of different frequencies that are frequency- and
phase-locked to the T0 DPLL. The OC6 output is LVDS/LVPECL. The OC3 output is CMOS/TTL. Altogether more
than 60 output frequencies are possible, ranging from 2kHz to 312.5MHz. The FSYNC output clock is always 8kHz,
and the MFSYNC output clock is always 2kHz.
7.2
Device Identification and Protection
The 16-bit read-only ID field in the ID1 and ID2 registers is set to 0C22h = 3106 decimal. The device revision can
be read from the REV register. Contact the factory to interpret this value and determine the latest revision. The
register set can be protected from inadvertent writes using the PROT register.
7.3
Local Oscillator and Master Clock Configuration
The T0 DPLL and the output DFS engines operate from a 204.8MHz master clock. The master clock is synthesized
from a 12.800MHz clock originating from a local oscillator attached to the REFCLK pin. The stability of the T0 DPLL
in free-run or holdover is equivalent to the stability of the local oscillator. Selection of an appropriate local oscillator
is therefore of crucial importance if the telecom standards listed in Table 1-1 are to be met. Simple XOs can be
used in less stringent cases, but TCXOs or even OCXOs may be required in the most demanding applications.
Careful evaluation of the local oscillator component is necessary to ensure proper performance. Contact Microsemi
timing products technical support for recommended oscillators.
The stability of the local oscillator is very important, but its absolute frequency accuracy is less important because
the DPLLs can compensate for frequency inaccuracies when synthesizing the 204.8MHz master clock from the
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3106LN+ | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 Line Card Timing IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| DS3107FP000 | 制造商:Thomas & Betts 功能描述:30A,CON,2P3W,MG,107,125V |
| DS3107FRAB0 | 制造商:Thomas & Betts 功能描述:30A,REC,2P3W,MG,107,AB0,125,SC |
| DS3107MP000 | 制造商:Thomas & Betts 功能描述:30A,PLG,2P3W,MG,107,125V |
| DS3107MP00K | 制造商:Thomas & Betts 功能描述:30A,PLG,2P3W,MG,107,125V,CC |
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