參數(shù)資料
型號(hào)： DS3106LN+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 19/92頁(yè)
文件大?。?/td> 0K
描述： IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 160
類型： 定時(shí)卡 IC，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum，電信
輸入： CMOS，TTL
輸出： CMOS，LVDS，LVPECL，TTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 312.5MHz
電源電壓： 1.62 V ~ 1.98 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 1429 (CN2011-ZH PDF)
DS3106
26
7.8.1 Signal Format Configuration
Output clock OC6 is an LVDS-compatible, LVPECL level-compatible outputs. The type of output can be selected or
the output can be disabled using the OC6SF configuration bits in the MCR8 register. The LVPECL level-compatible
mode generates a differential signal that is large enough for most LVPECL receivers. Some LVPECL receivers
have a limited common-mode signal range that can be accommodated for by using an AC-coupled signal. The
LVDS electrical specifications are listed in Table 10-4, and the recommended LVDS termination is shown in Figure
10-1. The LVPECL level-compatible electrical specifications are listed in Table 10-5, and the recommended
LVPECL receiver termination is shown in Figure 10-2. These differential outputs can be easily interfaced to LVDS,
LVPECL, and CML inputs on neighboring ICs using a few external passive components. See App Note HFAN-1.0
for details.
Output clocks OC3, FSYNC, and MFSYNC are CMOS/TTL signal format.
7.8.2 Frequency Configuration
The frequency of output clocks OC3 and OC6 is a function of the settings used to configure the components of the
T0 PLL paths. These components are shown in the detailed block diagram of Figure 7-1.
The DS3106 uses digital frequency synthesis (DFS) to generate various clocks. In DFS a high-speed master clock
(204.8MHz) is divided down to the desired output frequency by adding a number to an accumulator. The DFS
output is a coding of the clock output phase that is used by a special circuit to determine where to put the edges of
the output clock between the clock edges of the master clock. The edges of the output clock, however, are not
ideally located in time, resulting in jitter with an amplitude typically less than 1ns pk-pk.
7.8.2.1 T0 DPLL and Feedback DFS Details
See Figure 7-1. The T0 forward-DFS block uses the 204.8MHz master clock and DFS technology to synthesize
internal clocks from which the output and feedback clocks are derived.
The feedback DFS block synthesizes the appropriate locking frequencies for use by the phase-frequency detector
(PFD). See Section 7.4.2.
7.8.2.2 Output DFS and APLL Details
See Figure 7-1. The output clock frequencies are determined by two 2kHz/8kHz DFS blocks, two DIG12 DFS
blocks, and three APLL DFS blocks. The T0 APLL, the T0 APLL2, and the T4 APLL (and their output dividers) get
their frequency references from three associated APLL DFS blocks. All the output DFS blocks are connected to the
T0 DPLL.
The 2K8K DFS and FSYNC DFS blocks generate both 2kHz and 8kHz signals, which have about 1ns pk-pk jitter.
The FSYNC (8kHz) and MFSYNC (2 kHz) signals come from the FSYNC DFS block. The 2kHz and 8 kHz signals
that can be output on OC3 or OC6 always come from the 2K8K DFS.
The DIG1 DFS can generate an N x DS1 or N x E1 signal with about 1ns pk-pk jitter. The DIG2 DFS can generate
an N x DS1, N x E1, 6.312MHz, 10MHz, or N x 19.44MHz clock with approximately 1ns pk-pk jitter. The frequency
of the DIG1 clock is configured by the DIG1SS bit in MCR6 and the DIG1F[1:0] field in MCR7. The frequency of the
DIG2 clock is configured by the DIG2AF and DIG2SS bits in MCR6 and the DIG2F[1:0] field in MCR7. DIG1 and
DIG2 can be independently configured for any of the frequencies shown in Table 7-6 and Table 7-7, respectively.
The APLL DFS blocks and their associated output APLLs and output dividers can generate many different
frequencies. The T0 APLL frequencies that can be generated are listed in Table 7-9. The T0 APLL2 frequency is
always 312.500MHz. The T4 APLL frequencies that can be generated are listed in Table 7-11. The output
frequencies that can be generated from the APLL circuits are listed in Table 7-8.
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