IPU Reset (Activ" />
參數(shù)資料
型號(hào): DS3106LN+
廠商: Maxim Integrated Products
文件頁數(shù): 3/92頁
文件大小: 0K
描述: IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
類型: 定時(shí)卡 IC,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum,電信
輸入: CMOS,TTL
輸出: CMOS,LVDS,LVPECL,TTL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 312.5MHz
電源電壓: 1.62 V ~ 1.98 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS3106
11
Table 6-3. Global Pin Descriptions
PIN NAME
PIN DESCRIPTION
RST
IPU
Reset (Active Low). When this global asynchronous reset is pulled low, all internal circuitry is
reset to default values. The device is held in reset as long as
RST is low. RST should be held
low for at least two REFCLK cycles after the external oscillator has stabilized and is providing
valid clock signals.
SRCSW
IPD
Source Switching. Input reference selection pin. Selects IC3 when high and IC4 when low.
See Section 7.6.
TEST
IPD
Factory Test Mode Select. Wire this pin to VSS for normal operation.
IPF0
IPD
Input Frequency Select 0. Together with IPF1 and IPF2, this pin sets the default frequency of
the IC3 and IC4 input clock pins. The value is sampled when
RST goes high, and the
FREQ[3:0] fields of ICR3 and ICR4 are set accordingly. See Table 7-2. After
RST goes high this
pin is ignored.
IPF1
IPD
Input Frequency Select 1. Together with IPF0 and IPF2, this pin sets the default frequency of
the IC3 and IC4 input clock pins. The value is sampled when
RST goes high, and the
FREQ[3:0] fields of ICR3 and ICR4 are set accordingly. See Table 7-2. After
RST goes high this
pin is ignored.
IPF2
IPD
Input Frequency Select 2. Together with IPF0 and IPF1, this pin sets the default frequency of
the IC3 and IC4 input clock pins. The value is sampled when
RST goes high, and the
FREQ[3:0] fields of ICR3 and ICR4 are set accordingly. See Table 7-2. After
RST goes high this
pin is ignored.
O3F0
IPU
OC3 Frequency Select 0. This pin is sampled when the
RST pin goes high and the value is
used as O3F0, which, together with O3F2 and O3F1, sets the default frequency of the OC3
output clock pin. See Table 7-17. After
RST goes high this pin is ignored.
O3F1/SRFAIL
IOPU
OC3 Frequency Select 1/SRFAIL Status Pin. This pin is sampled when the
RST pin goes high
and the value is used as O3F1, which, together with O3F2 and O3F0, sets the default
frequency of the OC3 output clock pin. See Table 7-17. After
RST goes high, if MCR10:SRFPIN
= 1, this pin follows the state of the SRFAIL status bit in the MSR2 register. This gives the
system a very fast indication of the failure of the selected reference. When MCR10:SRFPIN = 0,
SRFAIL is disabled (high impedance).
O3F2/LOCK
IOPD
OC3 Frequency Select 2/T0 DPLL LOCK Status. This pin is sampled when the
RST pin goes
high and the value is used as O3F2, which, together with O3F1 and O3F0, sets the default
frequency of the OC3 output clock pin. See Table 7-17. After
RST goes high, if
MCR1.LOCKPIN = 1, this pin indicates the lock state of the T0 DPLL. When MCR1.LOCKPIN =
0, LOCK is disabled (low).
0 = Not locked
1 = Locked
O6F0/GPIO1
IOPD
OC6 Frequency Select 0/General-Purpose I/O Pin 1. This pin is sampled when the
RST pin
goes high and the value is used as O6F0, which, together with O6F2 and O6F1, sets the
default frequency of the OC6 output clock pin. See Table 7-16. After
RST goes high, this pin
can be used as a general-purpose I/O pin. GPCR:GPIO1D configures this pin as an input or an
output. GPCR:GPIO1O specifies the output value. GPSR:GPIO1 indicates the state of the pin.
O6F1/GPIO2
IOPD
OC6 Frequency Select 1/General-Purpose I/O Pin 2. This pin is sampled when the
RST pin
goes high and the value is used as O6F1, which, together with O6F2 and O6F0, sets the
default frequency of the OC6 output clock pin. See Table 7-16. After
RST goes high, this pin
can be used as a general-purpose I/O pin. GPCR:GPIO2D configures this pin as an input or an
output. GPCR:GPIO2O specifies the output value. GPSR:GPIO2 indicates the state of the pin.
O6F2/GPIO3
IOPU
OC6 Frequency Select 2/General-Purpose I/O Pin 3. This pin is sampled when the
RST pin
goes high and the value is used as O6F2, which, together with O6F1 and O6F0, sets the
default frequency of the OC6 output clock pin. See Table 7-16. After
RST goes high, this pin
can be used as a general-purpose I/O pin. GPCR:GPIO3D configures this pin as an input or an
output. GPCR:GPIO3O specifies the output value. GPSR:GPIO3 indicates the state of the pin.
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