參數(shù)資料
型號(hào)： DS3106LN+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 66/92頁(yè)
文件大?。?/td> 0K
描述： IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 160
類(lèi)型： 定時(shí)卡 IC，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum，電信
輸入： CMOS，TTL
輸出： CMOS，LVDS，LVPECL，TTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 312.5MHz
電源電壓： 1.62 V ~ 1.98 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 1429 (CN2011-ZH PDF)
DS3106
69
Register Name:
PHLIM1
Register Description:
Phase Limit Register 1
Register Address:
73h
Bit #
7
6
5
4
3
2
1
0
Name
FLEN
NALOL
1
—
FINELIM[2:0]
Default
1
0
1
0
1
0
Bit 7: Fine Phase Limit Enable (FLEN). This configuration bit enables the fine phase limit specified in the
FINELIM[2:0] field. The fine limit must be disabled for multi-UI jitter tolerance (see PHLIM2 fields). See Section
0 = Disabled
1 = Enabled
Bit 6: No Activity Loss-of-Lock (NALOL). The T0 and the T4 DPLLs can detect that an input clock has no activity
very quickly (within two clock cycles). When NALOL = 0, loss-of-lock is not declared when clock cycles are missing,
and nearest edge locking (
±180°) is used when the clock recovers. This gives tolerance to missing cycles. When
NALOL = 1, loss-of-lock is indicated as soon as no activity is detected, and the device switches to phase/frequency
locking (
±360°). See Sections 7.5.3 and 7.7.5.
0 = No activity does not trigger loss-of-lock.
1 = No activity does trigger loss-of-lock.
Bit 5: Leave set to 1 (test control).
Bits 2 to 0: Fine Phase Limit (FINELIM[2:0]). This field specifies the fine phase limit window, outside of which
loss-of-lock is declared. The FLEN bit enables this feature. The phase of the input clock has to be inside the fine
limit window for two seconds before phase lock is declared. Loss-of-lock is declared immediately if the phase of the
input clock is outside the phase limit window. The default value of 010 is appropriate for most situations. See
Section 7.7.5.
000 = Always indicates loss-of-phase lock—do not use
001 = Small phase limit window,
±45° to ±90°
010 = Normal phase limit window,
±90° to ±180° (default)
100, 101, 110, 111 = Proportionately larger phase limit window
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS3106LN+ 功能描述:計(jì)時(shí)器和支持產(chǎn)品 Line Card Timing IC RoHS:否 制造商:Micrel 類(lèi)型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel
DS3107FP000 制造商:Thomas & Betts 功能描述:30A,CON,2P3W,MG,107,125V
DS3107FRAB0 制造商:Thomas & Betts 功能描述:30A,REC,2P3W,MG,107,AB0,125,SC
DS3107MP000 制造商:Thomas & Betts 功能描述:30A,PLG,2P3W,MG,107,125V
DS3107MP00K 制造商:Thomas & Betts 功能描述:30A,PLG,2P3W,MG,107,125V,CC
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