參數(shù)資料
型號: DS3106LN+
廠商: Maxim Integrated Products
文件頁數(shù): 14/92頁
文件大?。?/td> 0K
描述: IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 160
類型: 定時卡 IC,多路復用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum,電信
輸入: CMOS,TTL
輸出: CMOS,LVDS,LVPECL,TTL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 312.5MHz
電源電壓: 1.62 V ~ 1.98 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-LQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS3106
21
Figure 7-2. T0 DPLL State Transition Diagram
FREE-RUN
(001)
PRE-LOCKED
(110)
RESET
SELECTED REFERENCE ACTIVE
SELECTED REFERENCE
INACTIVE > 2s
LOCKED
(100)
PHASE-LOCKED TO SELECTED
REFERENCE > 2s
LOSS-OF-
LOCK
(111)
HOLDOVER
(010)
LOSS-OF-LOCK ON
SELECTED REFERENCE
PHASE-LOCK REGAINED ON
SELECTED REFERENCE > 2s
PRE-LOCKED 2
(101)
SELECTED REFERENCE
INACTIVE > 2s
SELECTED REFERENCE SWITCH
SELECTED REFERENCE INACTIVE > 2s
SELECTED REFERENCE ACTIVE
SELECTED REFERENCE
INACTIVE > 2s
SELECTED REFERENCE SWITCH
SELECTED REFERENCE
PHASE-LOCKED > 2s
Note 1:
Phase lock is declared internally when the DPLL has maintained phase lock continuously for approximately 1 to 2 seconds.
Note 2:
When selected reference is invalid and the DPLL is not in free-run or holdover, the DPLL is in a temporary holdover state.
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