參數(shù)資料
型號： DS3106LN+
廠商： Maxim Integrated Products
文件頁數(shù)： 46/92頁
文件大?。?/td> 0K
描述： IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 160
類型： 定時(shí)卡 IC，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum，電信
輸入： CMOS，TTL
輸出： CMOS，LVDS，LVPECL，TTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 無/是
頻率 - 最大： 312.5MHz
電源電壓： 1.62 V ~ 1.98 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
產(chǎn)品目錄頁面： 1429 (CN2011-ZH PDF)
DS3106
50
Register Name:
MCR3
Register Description:
Master Configuration Register 3
Register Address:
34h
Bit #
7
6
5
4
3
2
1
0
Name
—
XOEDGE
FRUNHO
—
SONSDH
—
Default
1
0
see below
1
0
Bit 5: Local Oscillator Edge (XOEDGE). This bit specifies the significant clock edge of the local oscillator clock
signal on the REFCLK input pin. The faster edge should be selected for best jitter performance. See Section 7.3.
0 = Rising edge
1 = Falling edge
Bit 4: Free-Run Holdover (FRUNHO). When this bit is set to 1 the T0 DPLL holdover frequency is set to 0ppm so
the output frequency accuracy is set by the external oscillator accuracy. This affects both mini-holdover and the
holdover state.
0 = Digital holdover
1 = Free-run holdover, 0ppm
Bit 2: SONET or SDH Frequencies (SONSDH). This bit specifies the clock rate for input clocks with FREQ = 0001
in the ICR registers (20h to 28h). During reset the default value of this bit is latched from the SONSDH pin. See
Section 7.4.2.
0 = 2048kHz
1 = 1544kHz
Register Name:
MCR6
Register Description:
Master Configuration Register 6
Register Address:
38h
Bit #
7
6
5
4
3
2
1
0
Name
DIG2AF
DIG2SS
DIG1SS
—
Default
0
see below
1
Bit 7: Digital Alternate Frequency (DIG2AF). Selects alternative frequencies.
0 = Digital2 N x E1 or N x DS1 frequency specified by DIG2SS and MCR7:DIG2F.
1 = Digital2 6.312MHz, 10MHz, or N x 19.44MHz frequency specified by DIG2SS and MCR7:DIG2F.
Bit 6: Digital2 SONET or SDH Frequencies (DIG2SS). This bit specifies whether the clock rates generated by the
Digital2 clock synthesizer are multiples of 1.544MHz (SONET compatible) or multiples of 2.048MHz (SDH
compatible) or alternate frequencies. The specific multiple is set in the DIG2F field of the MCR7 register. When
RST = 0 the default value of this bit is latched from the SONSDH pin.
DIG2AF = 0:
0 = Multiples of 2048kHz
1 = Multiples of 1544kHz
DIG2AF = 1:
6.312MHz, 10MHz, or N x 19.44MHz
Bit 5: Digital1 SONET or SDH Frequencies (DIG1SS). This bit specifies whether the clock rates generated by the
Digital1 clock synthesizer are multiples of 1544kHz (SONET compatible) or multiples of 2048kHz (SDH
compatible). The specific multiple is set in the DIG1F field of the MCR7 register. When
RST = 0 the default value of
this bit is latched from the SONSDH pin.
0 = Multiples of 2048kHz
1 = Multiples of 1544kHz
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS3106LN+ 功能描述:計(jì)時(shí)器和支持產(chǎn)品 Line Card Timing IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel
DS3107FP000 制造商:Thomas & Betts 功能描述:30A,CON,2P3W,MG,107,125V
DS3107FRAB0 制造商:Thomas & Betts 功能描述:30A,REC,2P3W,MG,107,AB0,125,SC
DS3107MP000 制造商:Thomas & Betts 功能描述:30A,PLG,2P3W,MG,107,125V
DS3107MP00K 制造商:Thomas & Betts 功能描述:30A,PLG,2P3W,MG,107,125V,CC
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