參數(shù)資料
型號(hào): DS3106LN+
廠(chǎng)商: Maxim Integrated Products
文件頁(yè)數(shù): 69/92頁(yè)
文件大?。?/td> 0K
描述: IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
類(lèi)型: 定時(shí)卡 IC,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum,電信
輸入: CMOS,TTL
輸出: CMOS,LVDS,LVPECL,TTL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 無(wú)/是
頻率 - 最大: 312.5MHz
電源電壓: 1.62 V ~ 1.98 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 1429 (CN2011-ZH PDF)
DS3106
71
Register Name:
PHMON
Register Description:
Phase Monitor Register
Register Address:
76h
Bit #
7
6
5
4
3
2
1
0
Name
NW
Default
0
1
0
Bit 7: Low-Frequency Input Clock Noise Window (NW). For 2kHz, 4kHz, or 8kHz input clocks, this configuration
bit enables a
±5% tolerance noise window centered around the expected clock edge location. Noise-induced edges
outside this window are ignored, reducing the possibility of phase hits on the output clocks. This only applies to the
T0 DPLL and should be enabled only when the T0 DPLL is locked to an input and the 180
° phase detector is being
used (TEST1.D180=0).
0 = All edges are recognized by the T0 DPLL.
1 = Only edges within the
±5% tolerance window are recognized by the T0 DPLL.
Register Name:
PHASE1
Register Description:
Phase Register 1
Register Address:
77h
Bit #
7
6
5
4
3
2
1
0
Name
PHASE[7:0]
Default
0
Note: The PHASE1 and PHASE2 registers must be read consecutively. See Section 8.3.
Bits 7 to 0: Current DPLL Phase (PHASE[7:0]). The full 16-bit PHASE[15:0] field spans this register and the
PHASE2 register. PHASE is a two’s-complement signed integer that indicates the current value of the phase
detector. The value is the output of the phase averager. The averaged phase difference in degrees is equal to
PHASE
× 0.707. See Section 7.7.6.
Register Name:
PHASE2
Register Description:
Phase Register 2
Register Address:
78h
Bit #
7
6
5
4
3
2
1
0
Name
PHASE[15:8]
Default
0
Bits 7 to 0: Current DPLL Phase (PHASE[15:8]). See the PHASE1 register description.
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