參數(shù)資料
型號: DS3106LN+
廠商: Maxim Integrated Products
文件頁數(shù): 53/92頁
文件大?。?/td> 0K
描述: IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 160
類型: 定時卡 IC,多路復用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum,電信
輸入: CMOS,TTL
輸出: CMOS,LVDS,LVPECL,TTL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 312.5MHz
電源電壓: 1.62 V ~ 1.98 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-LQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS3106
57
Register Name:
DIVN1
Register Description:
DIVN Register 1
Register Address:
46h
Bit #
7
6
5
4
3
2
1
0
Name
DIVN[7:0]
Default
1
Note: The DIVN1 and DIVN2 registers must be read consecutively and written consecutively. See Section 8.3.
Bits 7 to 0: DIVN Factor (DIVN[7:0]). The full 16-bit DIVN[15:0] field spans this register and DIVN2. This field
contains the integer value used to divide the frequency of input clocks that are configured for DIVN mode. The
frequency is divided by DIVN[15:0] + 1. See Section 7.4.2.4.
Register Name:
DIVN2
Register Description:
DIVN Register 2
Register Address:
47h
Bit #
7
6
5
4
3
2
1
0
Name
DIVN[15:8]
Default
0
1
Bits 7 to 0: DIVN Factor (DIVN[15:8]). See the DIVN1 register description.
Register Name:
MCR10
Register Description:
Master Configuration Register 10
Register Address:
48h
Bit #
7
6
5
4
3
2
1
0
Name
SRFPIN
Default
1
0
1
0
Bit 6: SRFAIL Pin Enable (SRFPIN). When this bit is set to 1, the SRFAIL pin is enabled. When enabled the
SRFAIL pin follows the state of the SRFAIL status bit in the MSR2 register. This gives the system a very fast
indication of the failure of the current reference. See Section 7.5.3.
0 = SRFAIL pin disabled (high impedance)
1 = SRFAIL pin enabled
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