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| 型號(hào)： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁(yè)數(shù)： | 54/66頁(yè) |
| 文件大?。?/td> | 519K |
| 代理商： | DAC1617D1G0HN |
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DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
54 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.18.7
Page A bit definition detailed description
The tables in this section contain detailed descriptions of the page A registers.
Table 51.
Default values are shown highlighted.
Bit
Symbol
4
LD_PD
Register MAIN_CNTRL (address 00h)
Access
R/W
Value
Description
LVDS interface power-down (control possible only
when PD_CNTRL = 1)
switched on
switched off
power-down modes controlled by
DCMSU block
SPI registers
compensation delay controlled by
DCMSU block (automatic calibration)
SPI registers (manual control)
reset DCLK
disable
enable
reset LVDS clock
disable
0
1
3
PD_CNTRL
R/W
0
1
2
CAL_CNTRL
R/W
0
1
1
RST_DCLK
R/W
0
1
0
RST_LCLK
R/W
0
1
enable
Table 52.
Default values are shown highlighted.
Bit
Symbol
3 to 0
LDCLK_DEL[3:0]
Register MAN_LDCLKDEL (address 01h)
Access
R/W
Value
Description
LVDS clock compensation delay (control only if
CAL_CNTRL = 1)
4-bit compensation delay for LVDS clock
-
Table 53.
Default values are shown highlighted.
Bit
Symbol
3
SBER
Register DBG_LVDS (address 02h)
Access
R/W
Value
Description
simple BER control
no action
simple BER active
reserved
0
1
000
2 to 0
RESERVED
R/W
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