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| 型號(hào)： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁(yè)數(shù)： | 15/66頁(yè) |
| 文件大?。?/td> | 519K |
| 代理商： | DAC1617D1G0HN |
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DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
15 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.2.2
SPI timing description
The SPI interface can operate at a frequency up to 15 MHz. The SPI timings are shown in
Figure 4
.
The SPI timing characteristics are given in
Table 8
.
Table 8.
Symbol
f
SCLK
t
w(SCLK)
10.3 Power-on sequence
There are three steps for the power-on sequence (see
Figure 5
):
1. The board is power-on. At the turn-on time, all DAC1617D1G0 supplies have reached
their specification ranges.
2. At least 1
s after the turn-on time pin RESET_N must
be released.
3. When the DAC clock and LVDS clock are stable, the SPI configuration is sent to the
DAC1617D1G0. Writing 0 in bits RST_DCLK and RST_LCLK of the register
MAIN_CNTRL (see
Table 51
) starts the automatic calibration. 30
s after this
calibration, the DAC1617D1G0 is operational.
Fig 4.
SPI timing diagram
SPI timing characteristics
Parameter
SCLK frequency
SCLK pulse
width
SCS_N set-up
time
SCS_N hold
time
SDIO set-up
time
SDIO hold time
RESET_N pulse
width
Min
-
30
Typ
-
-
Max
25
-
Unit
MHz
ns
t
su(SCS_N)
20
-
-
ns
t
h(SCS_N)
20
-
-
ns
t
su(SDIO)
10
-
-
ns
t
h(SDIO)
t
w(RESET_N)
5
30
-
-
-
-
ns
ns
001aan830
50 %
t
w(RESET_N)
t
su(SCS_N)
t
su(SDIO)
t
h(SDIO)
t
h(SCS_N)
t
w(SCLK)
50 %
RESET_N
(optional)
SCS_N
SCLK
SDIO
50 %
50 %
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