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| 型號： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁數(shù)： | 27/66頁 |
| 文件大?。?/td> | 519K |
| 代理商： | DAC1617D1G0HN |
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DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
27 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Where:
M is the two’s complement coding representation of FREQ_NCO[39:0]
f
s
is the DAC clock sampling frequency
The default settings are:
f
NCO
= 96 MHz
f
s
= 640 Msps
Registers PHINCO_LSB and PHINCO_MSB over 16 bits from 0
to 360
(see
Table 31
)
can set the phase of the NCO.
10.9.2
NCO low power
The five MSB-bits of register FREQNCO_B4 (bits FREQ_NCO[39:35]; see
Table 25
) can
set the frequency, when using NCO low power (bit NCO_LP_SEL; see
Table 23
).
The frequency is calculated with
Equation 2
.
(2)
Where:
M is the two’s complement coding representation of FREQ_NCO[39:35]
f
s
is the DAC clock sampling frequency
The five MSB-bits of register PHINCO_MSB (see
Table 31
) can set the phase of the NCO
low power.
10.9.3
Complex modulator
The complex modulator upconverts the single side band by mixing NCO signals and I and
Q input signals.
Table 16
shows the various possibilities set by bits MODULATION[2:0] of
register TXCFG (see
Table 23
).
f
NCO
M
--------------
f
s
2
=
Table 16.
MODULATION[2:0]
000
001
Complex modulator operation mode
Mode
bypass
positive
upper ssb
positive
lower ssb
negative
upper ssb
negative
lower ssb
not defined
Path A
Path B
010
011
100
others
-
-
I t
Q t
I t
NCO
t
cos
Q t
NCO
t
sin
–
I t
NCO
t
sin
Q t
NCO
t
cos
+
I t
NCO
t
cos
Q t
NCO
t
sin
+
I t
NCO
t
sin
Q t
NCO
t
cos
–
I t
NCO
t
cos
Q t
NCO
t
sin
–
I t
–
NCO
t
sin
Q t
NCO
t
cos
–
I t
NCO
t
cos
Q t
NCO
t
sin
+
I t
–
NCO
t
sin
Q t
NCO
t
cos
+
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