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| 型號： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁數(shù)： | 43/66頁 |
| 文件大小： | 519K |
| 代理商： | DAC1617D1G0HN |
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DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
43 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
2
B_DGAIN_E
R/W
DAC B digital gain control
disable
enable
DAC attenuation control
unity gain
3 dB gain
Digital DAC output clipping control
disable
enable
0
1
1
MINUS_3DB
R/W
0
1
0
CLIPPING_ENA
R/W
0
1
Table 28.
Default values are shown highlighted.
Bit
Symbol
Register DAC_OUT_CTRL (address 0Fh)
…continued
Access
Value
Description
Table 29.
Default values are shown highlighted.
Bit
Symbol
7 to 0
CLIPPING_LEVEL[7:0]
Register DAC_CLIPPING (address 10h)
Access
R/W
Value
-
Description
Digital DAC output clipping level value
Table 30.
Default values are shown highlighted.
Address
Register
11h
DAC_A_OFFSET_LSB
Digital offset value registers (address 11h to 14h) bit description
Bit
7 to 0
Symbol
DAC_A_OFFSET[7:0]
Access
R/W
Value
Description
DAC A digital offset value
-
least significant 8 bits for the
DAC A digital offset
most significant 8 bits for the
DAC A digital offset
DAC B digital offset value
least significant 8 bits for the
DAC B digital offset
most significant 8 bits for the
DAC B digital offset
12h
DAC_A_OFFSET_MSB 7 to 0
DAC_A_OFFSET[15:8]
-
13h
DAC_B_OFFSET_LSB
7 to 0
DAC_B_OFFSET[7:0]
R/W
-
14h
DAC_B_OFFSET_MSB 7 to 0
DAC_B_OFFSET[15:8]
-
Table 31.
Default values are shown highlighted.
Address
Register
15h
PHINCO_LSB
NCO phase offset registers (address 15h to 16h) bit description
Bit
7 to 0
Symbol
PH_NCO[7:0]
Access
R/W
Value
Description
NCO phase offset LSB
least significant 8 bits for the NCO phase
setting
NCO phase offset MSB
most significant 8 bits for the NCO phase
setting
-
16h
PHINCO_MSB
7 to 0
PH_NCO[15:8]
R/W
-
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