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| 型號(hào)： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類(lèi)： | 外設(shè)及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁(yè)數(shù)： | 17/66頁(yè) |
| 文件大小： | 519K |
| 代理商： | DAC1617D1G0HN |
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DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
17 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Table 9.
Internal LVDS bus
10.4.3
Input port swapping
The LVDS DDR receiver block internally maps the incoming LVDS data bus into two
buses with a single data rate (
Figure 7
).
These two buses can be swapped internally using bit LDAB_SWAP of register
LD_CNTRL (see
Table 57
and
Figure 8
).
Input LVDS bus swapping
External LVDS bus
(WORD_SWAP = 0)
LD[15]P,N
LD[14]P,N
LD[13]P,N
LD[12]P,N
LD[11]P,N
LD[10]P,N
LD[9]P,N
LD[8]P,N
LD[7]P,N
LD[6]P,N
LD[5]P,N
LD[4]P,N
LD[3]P,N
LD[2]P,N
LD[1]P,N
LD[0]P,N
External LVDS bus
(WORD_SWAP = 1)
LD[0]P,N
LD[1]P,N
LD[2]P,N
LD[3]P,N
LD[4]P,N
LD[5]P,N
LD[6]P,N
LD[7]P,N
LD[8]P,N
LD[9]P,N
LD[10]P,N
LD[11]P,N
LD[12]P,N
LD[13]P,N
LD[14]P,N
LD[15]P,N
LDI[15]P,N
LDI[14]P,N
LDI[13]P,N
LDI[12]P,N
LDI[11]P,N
LDI[10]P,N
LDI[9]P,N
LDI[8]P,N
LDI[7]P,N
LDI[6]P,N
LDI[5]P,N
LDI[4]P,N
LDI[3]P,N
LDI[2]P,N
LDI[1]P,N
LDI[0]P,N
Fig 7.
LVDS DDR receiver mapping LDAB SWAP = 0
001aan393
A0
B0
A1
B1
A2
B2
A3
B3
LVDS
RECEIVER
LD[15..0]P/N
LCLKP/N
PA[15..0]
PB[15..0]
LCLK
A0
A1
to DAC A
to DAC B
A2
A3
B0
B1
B2
B3
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