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| 型號(hào)： | DAC1617D1G0HN |
| 廠(chǎng)商： | NXP Semiconductors N.V. |
| 元件分類(lèi)： | 外設(shè)及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁(yè)數(shù)： | 51/66頁(yè) |
| 文件大?。?/td> | 519K |
| 代理商： | DAC1617D1G0HN |
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DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
51 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
1 0 1
1 1 0
1 1 1
+20 %
+30 %
+40 %
Table 46.
BIAS[3:0]
Bias current control table
…continued
Deviation from nominal current
Table 47.
Default values are shown highlighted.
Bit
Symbol
7
DAC_B_PON
DAC_PON_SLEEP register (address 16h) bit description
Access
R/W
Value
-
0
1
Description
DAC B power control
power-down
power on
DAC B mode selection
normal operation
Sleep mode
commutator B control
disable (power-down)
enable
DAC B bleed current control
disable (power-down)
enable
DAC A power control
power-down
power on
DAC B mode selection
normal operation
Sleep mode
commutator A control
disable (power-down)
enable
DAC A bleed current control
disable (power-down)
enable
6
DAC_B_SLEEP
R
0
1
5
DAC_B_COM_PD
R
0
1
4
DAC_B_BLEED_PD
R
0
1
3
DAC_A_PON
R
0
1
2
DAC_A_SLEEP
R
0
1
1
DAC_A_COM_PD
R
0
1
0
DAC_A_BLEED_PD
R
0
1
Table 48.
Default values are shown highlighted.
Bit
Symbol
2 to 0
PLL_DIG_DELAY[2:0]
DAC_TEST_8 register (address 17h) bit description
Access
R/W
Value
-
Description
digital clock delay offset of PLL/CKGEN_DIV8
Table 49.
Default values are shown highlighted.
Bit
Symbol
2 to 0
PAGE[2:0]
SPI_PAGE register (address 1Fh) bit description
Access
R/W
Value
-
Description
SPI page address
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