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| 型號： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁數(shù)： | 18/66頁 |
| 文件大?。?/td> | 519K |
| 代理商： | DAC1617D1G0HN |
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DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
18 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.4.4
Input port formatting
The LVDS DDR input bus multiplexes two 16-bit streams. The LVDS receiver block
demultiplexes these two streams.
The two streams can carry two data formats:
Folded
Interleaved
The data format block is in charge of the data format adaptation (see
Figure 9
).
The DAC1617D1G0 can correctly decode the input stream using bit IQ_FORMAT of
register LD_CNTRL (see
Table 57
), because it can determine which format is used on the
LVDS DDR bus.
Table 10
shows the format mapping between the LVDS input data and the data sent to the
two DAC channels depending on the data format selected.
Table 10.
Data format
interleaved format (IQ_FORMAT = 1)
folded format (IQ_FORMAT = 0)
Fig 8.
LVDS DDR receiver mapping LDAB SWAP = 1
001aan394
A0
B0
A1
B1
A2
B2
A3
B3
LVDS
RECEIVER
LD[15..0]P/N
LCLKP/N
PA[15..0]
PB[15..0]
LCLK
B0
B1
to DAC A
to DAC B
B2
B3
A0
A1
A2
A3
Fig 9.
LVDS DDR data formats
001aan395
A0
B0
A1
B1
A2
B2
A3
B3
LVDS
RECEIVER
LD[15..0]P/N
LCLKP/N
PA[15..0]
PB[15..0]
LCLK
DATA
FORMAT
A0
A1
A2
A3
B0
B1
B2
B3
I0
I1
to DAC A
to DAC B
I2
I3
Q0
Q1
Q2
Q3
Folded and interleaved format mapping
Data bit mapping
In[15..0] = An[15..0]; Qn[15..0] = Bn[15..0]
In[15..8] = An[15..8]; In[7..0] = Bn[15..8]
Qn[15..8] = An[7..0]; Qn[7..0] = Bn[7..0]
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