參數(shù)資料
型號(hào)： DAC1617D1G0HN
廠商： NXP Semiconductors N.V.
元件分類： 外設(shè)及接口
英文描述： Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
封裝： DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813
文件頁數(shù)： 37/66頁
文件大?。?/td> 519K
代理商： DAC1617D1G0HN
DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
37 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
V
DDD(1V8)
(LVDS: pins 19 and 36)
V
DDA(3V3)
(pins 59 and 68)
Use at least two capacitors for each power pin decoupling. Locate these capacitors as
close as possible to the DAC1617D1G0 power pins.
The die pad is used for both the power dissipation and electrical grounding. Insert several
vias (typically 7
7) to connect the internal ground plane to the top layer die area.
10.18 Configuration interface
10.18.1
Register description
The DAC1617D1G0 incorporates more than the 32 SPI registers allowed by the address
value A[4:0]. It uses three SPI register pages (page_00, page_01, and page_0A), each
containing 32 registers. The 32nd register of each page indicates which page is currently
addressed (00h, 01h or 0Ah).
Page 00h (see
Table 21
) is dedicated to the main control of the DAC1617D1G0:
Mode selection
NCO control
Auxiliary DAC control
Gain/phase/offset control
Power-down control
Page 01h (see
Table 35
) is dedicated to:
Multi-Device Synchronization (MDS)
DAC analog core control (biasing current, Sleep mode)
Page 0Ah (see
Table 50
) is dedicated to the LVDS input interface configuration.
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