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| 型號： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁數(shù)： | 13/66頁 |
| 文件大?。?/td> | 519K |
| 代理商： | DAC1617D1G0HN |
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DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
13 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10. Application information
10.1 General description
The DAC1617D1G0 is a dual 16-bit DAC operating up to 1000 Msps. Each DAC consists
of a segmented architecture, comprising a 6-bit thermometer subDAC and a 10-bit binary
weighted subDAC.
A maximum input LVDS DDR data rate of up to 312.5 MHz and a maximum output
sampling rate of 1000 Msps ensure more flexibility for wide bandwidth and multi-carrier
systems. The internal 40-bit NCO of the DAC1617D1G0 simplifies the frequency selection
of the system. The DAC1617D1G0 provides
2,
4 or
8 interpolation filters that are
useful for removing the undesired images.
Each DAC generates two complementary current outputs on pins IOUTAP and IOUTAN
and pins IOUTBP and IOUTBN. These outputs provide a full-scale output current (I
O(fs)
) of
up to 34 mA. An internal reference is available for the reference current which is externally
adjustable using pin VIRES.
High resolution internal gain, phase and offset control provide outstanding image and
Local Oscillator (LO) signal rejection at the system analog modulator output.
Multiple device synchronization enables synchronization of the outputs of multiple DAC
devices. MDS guarantees a maximum skew of one output clock period between several
devices.
All functions can be set using an SPI interface.
10.2 Serial Peripheral Interface (SPI)
10.2.1
Protocol description
The DAC1617D1G0 serial interface is a synchronous serial communication port ensures
easy interface with many industry microprocessors. It provides access to the registers that
define the operating modes of the chip in both write and read mode.
This interface can be configured as a 3-wire type (pin SDIO as bidirectional pin) or 4-wire
type (pins SDIO and SDO as unidirectional pins, input and output port respectively). In
both configurations, SCLK acts as the serial clock and SCS_N as the serial chip select.
Figure 3
shows the SPI protocol. Each read/write operation is followed by an SCS_N
signal and enabled by a LOW assertion to drive the chip with 2 bytes to 5 bytes,
depending on the content of the instruction byte (see
Table 7
).
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| DAC1617D1G0HN-C1 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN72 - Bulk |
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| DAC1617D1G0IQM-DB | 制造商:Integrated Device Technology Inc 功能描述:BOARD - Boxed Product (Development Kits) |
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