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| 型號(hào)： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類(lèi)： | 外設(shè)及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁(yè)數(shù)： | 30/66頁(yè) |
| 文件大?。?/td> | 519K |
| 代理商： | DAC1617D1G0HN |
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DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
30 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.12.2
Full-scale current adjustment
The default full-scale current (I
O(fs)
) is 20 mA but further adjustments can be made to both
DACs independently via the serial interface from 8.1 mA to 34 mA.
The settings applied to DAC_A_GAIN[9:0] (registers 17h and 18h; see
Table 32
) define
the full-scale current of DAC A:
(7)
The DAC_B_GAIN[9:0] (registers 19h and 1Ah; see
Table 32
;) define the full-scale current
of DAC B:
(8)
10.13 Digital offset adjustment
The DAC1617D1G0 provides digital offset correction (bits DAC_A_OFFSET[15:0] in
Table 30
) which can be used to adjust the common-mode level at the output of each DAC.
It adds an offset at the end of the digital part, just before the DACs.
Table 19
shows the
range of variation of the digital offset.
Table 19.
DAC_A_OFFSET[15:0]
DAC_B_OFFSET[15:0]
(two’s complement)
1000 0000 0000 0000
1000 0000 0000 0001
...
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0001
...
0111 1111 1111 1110
0111 1111 1111 1111
10.14 Analog output
The device has two output channels, producing two complementary current outputs,
which enable the reduction of even-order harmonics and noise. The pins are
IOUTAP/IOUTAN and IOUTBP/IOUTBN. Connect these pins via a load resistor R
L
to the
3.3 V analog power supply (V
DDA(3V3)
).
Figure 21
shows the equivalent analog output circuit of one DAC. This circuit includes a
parallel combination of NMOS current sources and associated switches for each
segment.
I
O fs
A
8100
DAC_A_GAIN[9:0]
25.3
+
=
I
O fs
A
8100
DAC_B_GAIN[9:0]
25.3
+
=
Digital offset adjustment
Offset applied
32768
32767
...
1
0
+1
...
+32766
+32767
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