- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄382924 > DAC1617D1G0HN (NXP Semiconductors N.V.) Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating PDF資料下載
參數(shù)資料
| 型號(hào)： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁(yè)數(shù)： | 41/66頁(yè) |
| 文件大小： | 519K |
| 代理商： | DAC1617D1G0HN |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)當(dāng)前第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)
DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
41 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
1 to 0
INTERPOLATION[1:0]
R/W
interpolation
no interpolation
2 interpolation
4 interpolation
8 interpolation
00
01
10
11
Table 23.
Default values are shown highlighted.
Bit
Symbol
Register TXCFG (address 01h) bit description
…continued
Access
Value
Description
Table 24.
Default values are shown highlighted.
Bit
Symbol
7
PLL_BP
Register PLLCFG (address 02h) bit description
Access
R/W
Value
Description
PLL bypass
DAC clock generated by PLL
DAC clock provided via external pins CLKN and
CLKP (PLL bypass mode)
PLL test buffer control
Power-down mode
enabled
PLL and CKGEN control
Power-down mode
0
1
6
PLL_BUF_PD
R/W
0
1
5
PLL_PLL_PD
R/W
0
1
enable
PLL divider factor
f
s
= 2
f
data
f
s
= 4
f
data
f
s
= 8
f
undefined
PLL phase shift
0 degrees phase shift of f
s
120 degrees phase shift of f
s
240 degrees phase shift of f
s
240 degrees phase shift of f
s
PLL oscillator output power-down
Power-down mode
enabled
4 to 3
PLL_DIV[1:0]
R/W
00
01
10
11
2 to 1
PLL_PHASE[1:0]
R/W
00
01
10
11
0
PLL_OSC_PD
R/W
0
1
Table 25.
Default values are shown highlighted.
Address
Register
04h
FREQNCO_B0
NCO frequency registers (address 04h to 08h) bit description
Bit
7 to 0
Symbol
FREQ_NCO[7:0]
Access
R/W
Value
Description
NCO frequency (two’s complement
coding)
least significant 8 bits for the NCO
frequency setting
intermediate 8 bits for the NCO
frequency setting
-
05h
FREQNCO_B1
7 to 0
FREQ_NCO[15:8]
R/W
-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DAC1617D1G0HN | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| DAC1627D1G25HN | Dual 16-bit DAC, up to 1.25 Gsps; 2x 4x and 8x interpolating |
| DAC1627D1G25 | |
| DAC1627D1G25HN | Dual 16-bit DAC, up to 1.25 Gsps; 2x 4x and 8x interpolating |
| DAN2222E | SWITCHING DIODE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC1617D1G0HN-C1 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN72 - Bulk |
| DAC1617D1G0HN-C18 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN72 - Tape and Reel |
| DAC1617D1G0IQM-DB | 制造商:Integrated Device Technology Inc 功能描述:BOARD - Boxed Product (Development Kits) |
| DAC161K87B WAF | 制造商:ON Semiconductor 功能描述: |
| DAC161P997 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DAC161P997 Single-Wire 16-bit DAC for 4-20mA Loops |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。