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| 型號： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁數(shù)： | 23/66頁 |
| 文件大?。?/td> | 519K |
| 代理商： | DAC1617D1G0HN |
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DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
23 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
[1]
Bits CDI_MODE[1:0] of register MISC_CNTRL (see
Table 58
).
[2]
Bits INTERPOLATION[1:0] of register TXCFG (see
Table 23
).
[3]
If a Single Sideband Modulator (SSBM) is used, see bits NCO_ON and MODULATION[2:0] of register TXCFG (see
Table 23
).
[4]
Pins CLKP and CLKN (see
Figure 2
).
[5]
Bit PLL_PD of register PLLCFG (see
Table 24
).
[6]
Bits PLL_DIV[1:0] of register PLLCFG (see
Table 24
).
10.7.2
CDI mode 1 (x4 interpolation)
CDI mode 1 (
4 interpolation) is required when the values of the LVDS DDR clock and the
internal CDI frequency are equal.
Table 13
shows examples of applications using an
internal PLL or an external clock for the DAC core.
[1]
Bits CDI_MODE[1:0] of register MISC_CNTRL (see
Table 58
).
[2]
Bits INTERPOLATION[1:0] of register TXCFG (see
Table 23
).
[3]
If SSBM is used, see bits NCO_ON and MODULATION[2:0] of register TXCFG (see
Table 23
).
[4]
Pins CLKP and CLKN (see
Figure 2
).
[5]
Bit PLL_PD of register PLLCFG (see
Table 24
).
[6]
Bits PLL_DIV[1:0] of register PLLCFG (see
Table 24
).
Table 12.
LVDS DDR
rate (MHz)
CDI mode 0: operating modes examples
I rate;
Q rate
(Msps)
CDI
mode
[1]
FIR mode
[2]
SSBM
rate
[3]
(Msps)
DAC rate
(Msps)
PLL configuration
PLL
status
[5]
DAC input
clock
[4]
(MHz)
320
640
PLL
divider
[6]
320
320
320
320
0
0
2
2
640
640
640
640
enabled
disabled
2
n.a.
Table 13.
LVDS DDR
rate (MHz)
CDI mode 1: operating modes examples
I rate;
Q rate
(Msps)
CDI
mode
[1]
FIR mode
[2]
SSBM
rate
[3]
(Msps)
DAC rate
(Msps)
PLL configuration
PLL
status
[5]
DAC input
clock
[4]
(MHz)
250
1000
PLL
divider
[6]
250
250
250
250
1
1
4
4
1000
1000
1000
1000
enabled
disabled
4
n.a.
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