參數(shù)資料
型號(hào)： CL-PS7111-VC-A
廠商： CIRRUS LOGIC INC
元件分類： 外設(shè)及接口
英文描述： Low-Power System-on-a-Chip
中文描述： MULTIFUNCTION PERIPHERAL, PQFP208
封裝： VQFP-208
文件頁(yè)數(shù)： 90/105頁(yè)
文件大?。?/td> 1207K
代理商： CL-PS7111-VC-A
September 1997
89
PRELIMINARY DATA BOOK v2.0
ELECTRICAL SPECIFICATIONS
CL-PS7111
Low-Power System-on-a-Chip
6.6.4
Pin Test Mode
This mode is selected by NTEST0 = 0, NTEST1 = 0, Latched NURESET = 1.
This test mode allows a simple ICT or MDA tester to check if all pins on the CL-PS7111 are correctly sol-
dered to the PCB. This mode does this by back-driving each pin in turn and checking the response on one
designated pin (the COL7 pin).
A parity bit is generated and output on the COL7 pin; this parity bit is the XOR of the input from every
CL-PS7111 signal pin except for the two test inputs. The input pad of each signal is fed into this XOR gate
regardless of signal type. Externally driving (back-driving) any signal pin from its reset state causes a tran-
sition of the COL7 pin.
Table 6-4
defines the rest state for all CL-PS7111 output pins. As Pin Test mode
is entered, the states of all CL-PS7111 inputs are latched, and forced back out on the pins. Thus ALL pins
(except the two test pins) are configured as outputs in this mode. This ensures only a ‘good’ solder joint
passes the pin test. When not in Pin Test mode, the XOR chain is disabled and cannot toggle to save
power.
It is essential in Pin Test mode that the NURESET pin is kept in the default (HIGH) state except when it
is being tested itself. This ensures that NPOR can be safely included in the pin test chain without affecting
the test mode.
6.6.5
High-Z (System) Test Mode
This mode selected by NTEST0 = 0, NTEST1 = 0, Latched NURESET = 0.
This test mode asynchronously disables all output buffers on the CL-PS7111, removing the CL-PS7111
signal from the PCB so that other devices on the PCB can be tested. The internal state of the CL-PS7111
is not altered directly by this test mode.
a
These inputs are INVERTED before being passed to the PLL to ensure that the default state of the port
(all ‘0’) maps onto the correct default state of the PLL (TSEL = 1, XTALON = 1, PLLON = 1, D0 = 0, D1
= 1, PLLBP = 0). This state produces the correct frequencies as shown. Any other combinations are for
testing the oscillator and PLL and should not be used in the circuit.
PLLON
a
I
PA3
Enable to PLL circuit
DN0
I
PA2
Selects other frequencies from PLL with DN0
DN1
a
I
PA1
Selects other frequencies from PLL with DN1
PLLBP
I
PA0
Bypasses PLL
RTCCLK
O
COL0
Output of RTC oscillator
CLK1
O
COL1
1-Hz clock from RTC divide chain
OSC36
O
COL2
36-MHz PLL main output
CLK576K
O
COL4
576 kHz divided-down as above
VTEST
O
COL5
Analog output of VCO loop filter
VREF
O
COL6
VCO output for test
Table 6-4.
Oscillator and PLL Test Mode Signals
(cont.)
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