參數(shù)資料
型號(hào)： CL-PS7111-VC-A
廠商： CIRRUS LOGIC INC
元件分類： 外設(shè)及接口
英文描述： Low-Power System-on-a-Chip
中文描述： MULTIFUNCTION PERIPHERAL, PQFP208
封裝： VQFP-208
文件頁(yè)數(shù)： 40/105頁(yè)
文件大?。?/td> 1207K
代理商： CL-PS7111-VC-A
September 1997
39
PRELIMINARY DATA BOOK v2.0
FUNCTIONAL DESCRIPTION
CL-PS7111
Low-Power System-on-a-Chip
Table 3-14
summarizes the external interrupt source latencies.
For the case of the keyboard interrupt, the following options are available and are selectable according to
bits 1 and 3 of the SYSCON2 register. Refer to the description of SYSCON2 in
Section 5.38 on page 70
for details.
G
If the KBWEN bit (SYSCON2[3]) is set low, then a keypress will cause a transition from a power saving state
if the keyboard interrupt is non-masked. When KBWEN is high, a keypress will cause the device to wake up
irrespective of the status of the Interrupt Mask Register.
G
When the KBD6 bit (SYSCON2[1]) is low, all eight of Port A inputs are OR’ed together to produce the internal
wake-up signal and keyboard interrupt request. This is the default reset state. When the KBD6 bit is high,
only the lowest six bits of Port A are OR’ed together to produce the internal wake-up signal and keyboard
interrupt request. The two most-significant bits of Port A are available as GPIO when this bit is set high.
If the keyboard-direct wake-up functionality is enabled (KBWEN bit is high), then the CL-PS7111 is guar-
anteed to exit from any power saving mode when a key is pressed, and a keyboard interrupt may be gen-
erated depending on the state of Interrupt Mask Register 2 (INTMR2[0]). If the KBWEN bit is set low then
the CL-PS7111 will only wake up if INTMR2[0] is set high. In the case where KBWEN is low and the
INTMR2[0] is low, it will only be possible to wake the device up using the external wake-up pin or another
enabled interrupt source. The keyboard interrupt capability allows an O/S to use a polled or interrupt-
driven keyboard routine, or a combination of both.
3.14
Resets
There are three asynchronous resets to the CL-PS7111: NPOR, NPWRFL, and NURESET. If any of these
resets are active, a system reset is internally generated. This clears all internal registers in the CL-PS7111
to ‘0’, except DRFPR (DRAM Refresh Period register) and RTC data and match registers, which are only
cleared by an active NPOR signal. Also, FBADDR is reset to give a default frame buffer start address of
0xC000 0000. Any reset also resets the ARM710a and allows it to begin execution at the reset vector
when the CL-PS7111 returns to the operating state.
Internal to the CL-PS7111, three different signals are used to reset storage elements: NPOR, NSYSRES,
and NSTBY. NPOR is an external signal and NSTBY is equivalent to the external RUN signal.
Table 3-14. External Interrupt Source Latencies
Interrupt Pin
Input State
Normal Mode
Latency
Idle Mode Latency
Standby Mode
Latency
NEXTFIQ
Not deglitched. Must
be active for 20
μ
s to
be detected.
Worst case latency of
20
μ
s.
Worst-case latency of
20
μ
s; if only single-cycle
instructions, less than 1
μ
s.
Including PLL/oscillator
settling time, approxi-
mately 0.25 sec. or < 1
μ
s if in 13-MHz mode
with CLENSL set.
NEINT[1–2]
Not deglitched.
Worst case latency of
20
μ
s.
As above.
As above.
EINT[3]
Not deglitched.
Worst case latency of
20
μ
s.
As above.
As above.
MEDCHG
Deglitched by 16-kHz
clock. Must be active
for at least 80
μ
s to be
detected.
Worst case latency of
80
μ
s.
Worst-case latency of
80
μ
s; if only single cycle
instructions, 60
μ
s.
As above. Note difference
if in 13-MHz mode with
CLKENSL set.
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