參數(shù)資料
型號(hào)： CL-PS7111-VC-A
廠商： CIRRUS LOGIC INC
元件分類： 外設(shè)及接口
英文描述： Low-Power System-on-a-Chip
中文描述： MULTIFUNCTION PERIPHERAL, PQFP208
封裝： VQFP-208
文件頁(yè)數(shù)： 48/105頁(yè)
文件大?。?/td> 1207K
代理商： CL-PS7111-VC-A
September 1997
47
PRELIMINARY DATA BOOK v2.0
REGISTER DESCRIPTIONS
CL-PS7111
Low-Power System-on-a-Chip
5.1
Port A Data Register — PADR
Values written to this 8-bit read/write register are output on the Port A pins if the corresponding data direc-
tion bits are set high (port output). Values read from this register reflect the external state of Port A, not
necessarily the value written to it. All bits are cleared by a system reset.
5.2
Port B Data Register — PBDR
Values written to this 8-bit read/write register are output on the Port B pins if the corresponding data direc-
tion bits are set high (port output). Values read from this register reflect the external state of Port B, not
necessarily the value written to it. All bits are cleared by a system reset.
5.3
Port D Data Register — PDDR
Values written to this 8-bit read/write register are output on the Port D pins if the corresponding data direc-
tion bits are set low (port output). Values read from this register reflect the external state of Port D, not
necessarily the value written to it. All bits are cleared by a system reset.
NOTE:
There is no Port C on the CL-PS7111.
5.4
Port A Data Direction Register — PADDR
Bits set in this 8-bit read/write register select the corresponding pin in Port A to become an output; clearing
any bit sets the pin to input. All bits are cleared by a system reset.
5.5
Port B Data Direction Register — PBDDR
Bits set in this 8-bit read/write register select the corresponding pin in Port B to become an output; clearing
a bit sets the pin to input. All bits are cleared by a system reset.
5.6
Port D Data Direction Register — PDDDR
Bits cleared in this 8-bit read/write register select the corresponding pin in Port D to become an output;
setting a bit sets the pin to input. All bits are cleared by a system reset so that Port D is output by default.
5.7
Port E Data Register — PEDR
Values written to this 3-bit read/write register are output on Port E pins if the corresponding data direction
bits are set high (port output). Values read from this register reflect the external state of Port E, not nec-
essarily the value written to it. All bits are cleared by a system reset.
5.8
Port E Data Direction Register — PEDDR
Bits set
in this 3-bit read/write register select the corresponding pin in Port E to become an output; clearing
a bit sets the pin to input. All bits are cleared by a system reset so that the default for Port E is input.
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