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參數(shù)資料
| 型號： | CL-PS7111-VC-A |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Low-Power System-on-a-Chip |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP208 |
| 封裝： | VQFP-208 |
| 文件頁數(shù)： | 68/105頁 |
| 文件大?。?/td> | 1207K |
| 代理商： | CL-PS7111-VC-A |
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September 1997
67
PRELIMINARY DATA BOOK v2.0
REGISTER DESCRIPTIONS
CL-PS7111
Low-Power System-on-a-Chip
5.23
Synchronous Serial ADC Interface Data Register —
SYNCIO
SYNCIO is a 16-bit read/write register. The data written to the SYNCIO register configures the SSI, and
the least-significant byte is serialized and transmitted out of the synchronous serial interface to configure
an external ADC, bit D7 (the MSB) first. The transfer clock automatically starts at the programmed fre-
quency, and a synchronization pulse is issued. The ADCIN pin is sampled on every clock edge, and the
result is shifted in to the SYNCIO read register.
During data transfer the SSIBUSY bit is set high, at the end of a transfer the SSEOTI interrupt is asserted.
This interrupt is cleared by reading the SYNCIO register. The data read from the SYNCIO register is the
lastsixteen bits shifted out of the ADC. The length of the data frame can be programmed by writing to the
SYNCIO register, this allows many different ADCs to be accommodated. The bits in the SYNCIO register
are defined as follows.
24:15
14
13
12:8
7:0
Reserved
TXFRMEN
SMCKEN
Frame length
ADC Configuration byte
Bit
Description
24:15
Reserved
14
TXFRMEN:
Setting this bit causes an ADC data transfer to be initiated; the value in the ADC configuration field is
shifted out to the ADC, and depending on the frame length programmed, a number of bits is captured from the ADC. If
the SYNCIO register is written to with the TXFRMEN bit low, no ADC transfer occurs, but the Frame length and
SMCKEN bits are affected.
13
SMCKEN:
Setting this bit enables a free-running sample clock at the programmed ADC clock frequency to be output
on the SMPLCK pin.
12:8
Frame Length:
The 5-bit Frame length field is the total number of shift clocks required to complete a data transfer. For
many ADCs this is 25, 8 for configuration byte + 1 null bit + 16 bits.
7:0
ADC Configuration:
8-bit configuration data to be sent to the ADC.
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