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參數(shù)資料
| 型號： | CL-PS7111-VC-A |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 外設及接口 |
| 英文描述： | Low-Power System-on-a-Chip |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP208 |
| 封裝： | VQFP-208 |
| 文件頁數(shù)： | 88/105頁 |
| 文件大?。?/td> | 1207K |
| 代理商： | CL-PS7111-VC-A |
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September 1997
87
PRELIMINARY DATA BOOK v2.0
ELECTRICAL SPECIFICATIONS
CL-PS7111
Low-Power System-on-a-Chip
6.5
I/O Buffer Characteristics
All I/O buffers on the CL-PS7111 are CMOS threshold input bidirectional buffers except the oscillator and
power pads. The output buffer is only enabled during pin test mode for signals that are normally inputs.
All output buffers are disabled during System Test (High-Z) mode. All buffers have a standard CMOS
threshold input stage apart from the Schmitt inputs and CMOS, slew-rate-controlled output stages to
reduce system noise.
Table 6-1
defines the I/O buffer output characteristics, which apply across the full
range of voltage and temperature (2.7 V and 0 to +70
o
C).
NOTES:
1)
All propagation delays are specified at 50%
VDD
to 50%
VDD
; all rise times are specified as 10%
VDD
to 90%
VDD
, and all fall times are specified as 90%
VDD
to 10%
VDD
.
2)
Pull-up current = 50
μ
A typical at
VDD
= 3.3 volts.
6.6
Test Modes
The CL-PS7111 supports a number of hardware-activated test modes; these are activated by the pin
combinations shown in
Table 6-2
. All latched signals only alter test modes while NPOR is low, and their
state is latched on the rising edge of NPOR. This allows these signals to be used normally during various
test modes (for example, the NURESET input can be used normally when the device is set into Functional
Test (EPB) mode).
Within each test mode a selection of pins are used as multiplexed outputs or inputs to provide/monitor the
test signals unique to that mode.
Table 6-1.
I/O Buffer Output Characteristics
Buffer Type
Drive Current
Propagation Delay (MAX)
Rise Time
(MAX)
Fall Time
(MAX)
Load
I/O strength 1
±
3 mA
15 ns
20 ns
15 ns
50 pF
I/O strength 2
±
12 mA
12 ns
16 ns
13 ns
50 pF
Table 6-2.
CL-PS7111 Hardware Test Modes
Test Mode
Latched
MEDCHG
Latched
PE0
Latched
NURESET
NTEST0
NTEST1
Normal operation (32-bit boot)
0
0
X
1
1
Normal operation (8-bit boot)
0
1
X
1
1
Alternative test ROM boot
1
X
X
1
1
Oscillator/PLL bypass
X
X
X
1
0
Functional Test (EPB)
X
X
1
0
1
Oscillator/PLL Test
X
X
0
0
1
Pin Test
X
X
1
0
0
System Test (all High-Z)
X
X
0
0
0
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