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參數(shù)資料
| 型號： | CL-PS7111-VC-A |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Low-Power System-on-a-Chip |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP208 |
| 封裝： | VQFP-208 |
| 文件頁數(shù)： | 31/105頁 |
| 文件大?。?/td> | 1207K |
| 代理商： | CL-PS7111-VC-A |
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PRELIMINARY DATA BOOK v2.0
September 1997
30
FUNCTIONAL DESCRIPTION
CL-PS7111
Low-Power System-on-a-Chip
PSLEEP pin of the CL-PS6700, allowing them to be put into a power saving state before the CL-PS7111
enters standby mode.
NOTE:
It is essential that the software monitors the appropriate status registers within the CL-PS6700 to ensure no
pending posted bus transactions before standby mode is entered. Failure to do this will result in incomplete
PCMCIA accesses.
3.9
DRAM Controller
The DRAM controller in the CL-PS7111 allows all connections to directly interface up to two banks of
DRAM. The width of the memory interface is programmable to 16-bit or 32-bit. The two banks have to be
the same width. Each bank can be up to 256 Mbytes. Two RAS lines and four CAS lines are provided, one
CAS line per byte line. CAS0 enables D[7:0] in little-endian as well as big-endian modes. The DRAM
device size is not programmable. Therefore, devices used that are smaller than the largest size supported
(1-Gbit), lead to a segmented memory map, each bank being separated by 256 Mbytes. Segments
smaller than the bank size repeat within the bank.
Table 3-9
shows the mapping of physical address-to-
DRAM row and column address. This mapping has been organized to support any DRAM device size
from 4--Mbit to 1-Gbit with a ‘square’ row and column configuration (the number of column addresses
equals the number of row addresses). If a non-square DRAM is used, further fragmentation of the mem-
ory map can occur, although the smallest contiguous segment is always 1-Mbyte. With proper mapping
of pages and sections by the MMU, contiguous memory blocks can be created.
The DRAM controller breaks all sequential access that the minimum page sizes defined support.
a
This bit will be generated by the DRAM controller.
Table 3-9.
Physical-to-DRAM Address Mapping
Memory
Address
DRAM
Column
×
16 mode
DRAM
Column
×
32 mode
DRAM Row
×
16 mode
DRAM Row
×
32 mode
Pin Name
0
A1
a
A2
A9
A10
A27/DRA0
1
A2
A3
A10
A11
A26/DRA1
2
A3
A4
A11
A12
A25/DRA2
3
A4
A5
A12
A13
A24/DRA3
4
A5
A6
A13
A14
A23/DRA4
5
A6
A7
A14
A15
A22/DRA5
6
A7
A8
A15
A16
A21/DRA6
7
A8
A9
A16
A17
A20/DRA7
8
A18
A19
A17
A18
A19/DRA8
9
A20
A21
A19
A20
A18/DRA9
10
A22
A23
A21
A22
A17/DRA10
11
A24
A25
A23
A24
A16/DRA11
12
A26
A27
A25
A26
A15/DRA12
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