- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379891 > CL-PS7111-VC-A (CIRRUS LOGIC INC) Low-Power System-on-a-Chip PDF資料下載
參數(shù)資料
| 型號(hào)： | CL-PS7111-VC-A |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Low-Power System-on-a-Chip |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP208 |
| 封裝： | VQFP-208 |
| 文件頁(yè)數(shù)： | 66/105頁(yè) |
| 文件大?。?/td> | 1207K |
| 代理商： | CL-PS7111-VC-A |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)當(dāng)前第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)
September 1997
65
PRELIMINARY DATA BOOK v2.0
REGISTER DESCRIPTIONS
CL-PS7111
Low-Power System-on-a-Chip
5.22
UART Bit Rate and Line Control Registers — UBRLCR1–2
The UART Bit Rate and Line Control registers are 19-bit read/write registers. A write to these registers
sets the bit rate and mode of operation for the internal UARTs.
31:19
18:17
16
15
14
13
12
11:0
Reserved
WRDLEN
FIFOEN
XSTOP
EVENPRT
PRTEN
BREAK
Bit rate divisor
Bit
Description
31:19
Reserved
18:17
WRDLEN:
This 2-bit field selects the word length as shown in the following table.
16
FIFOEN:
Set to enable FIFO buffering of Rx and Tx data. Clear to disable the FIFO, that is, set its depth to one byte.
15
XSTOP:
Extra stop bit. Setting this bit causes the UART to transmit two stop bits after each data byte, clearing it trans-
mits one stop bit after each data byte.
14
EVENPRT:
Even parity bit. Setting this bit sets parity generation and checking to even parity, clearing it sets odd parity.
This bit has no effect if the PRTEN bit is clear.
13
PRTEN:
Parity enable bit. Setting this bit enables parity detection and generation.
12
BREAK:
Setting this bit drives the Tx output active (high) to generate a break.
Bit
Word Length
18
17
0
0
5 bits
0
1
6 bits
1
0
7 bits
1
1
8 bits
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CL-PS7500FE | System-on-a Chip for Internet Appliance |
| CL-SH8665 | Integrated ATA Drive microcontroller(集成ATA驅(qū)動(dòng)微控制器) |
| CL1431 | Precision Adjustable Shunt Reference |
| CL1431D | Precision Adjustable Shunt Reference |
| CL1431LP | Precision Adjustable Shunt Reference |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CL-PS7500FE | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:System-on-a Chip for Internet Appliance |
| CLPT-12SP-06 | 制造商:Tri-Star Electronics International 功能描述:CONNECTOR - Bulk |
| CLPT-12SP-67 | 制造商:Tri-Star Electronics International 功能描述:- Bulk |
| CL-PU/O | 制造商:Maxell 功能描述:Couleur® Stereo Ear Buds w/ Multi-Size Ear Tips - Purple/Orange |
| CL-PX0070-30QC-A | 制造商:Cirrus Logic 功能描述:TRAY OF 19 3 OF THEM SLIGHTLY BENT LEADS |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。