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| 型號(hào)： | CL-PS7111-VC-A |
| 廠(chǎng)商： | CIRRUS LOGIC INC |
| 元件分類(lèi)： | 外設(shè)及接口 |
| 英文描述： | Low-Power System-on-a-Chip |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP208 |
| 封裝： | VQFP-208 |
| 文件頁(yè)數(shù)： | 67/105頁(yè) |
| 文件大?。?/td> | 1207K |
| 代理商： | CL-PS7111-VC-A |
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PRELIMINARY DATA BOOK v2.0
September 1997
66
REGISTER DESCRIPTIONS
CL-PS7111
Low-Power System-on-a-Chip
11:0
Bit Rate Divisor:
This 12-bit field set the bit rate. If the system is operating with an 18.432-MHz master clock, then the
bit rate divider is fed by a clock frequency of 3.6864 MHz, which is then further divided internally by 16 to give the bit
rate. The formula to give the divisor value for any bit rate when operating from the 18.432-MHz clock is:
Divisor = (230400
÷
bit rate)
1
Equation 5-9
A value of ‘0’ in this field is illegal when in the 18.432-MHz mode. In 13-MHz mode, the clock frequency fed to the
UART is 1.8571 MHz. In this mode, ‘0’ is a legal divisor value and generates the maximum possible bit rate. The follow-
ing tables show example bit rates with the corresponding divisor value.
Bit
Description
(cont.)
Table 5-3.
UART Bit Rates at
18.432-MHz Clock Rate
Divisor
Value
Bit Rate at
18.432 MHz
0
—
1
115200
2
76800
3
57600
5
38400
11
19200
15
14400
23
9600
95
2400
191
1200
2094
110
Table 5-4.
UART Bit Rates at 13-MHz
Clock Rate
Divisor
Value
Bit Rate
at 13 MHz
Error on
13-MHz value
0
116071
0.75%
1
58036
0.75%
2
38690
0.75%
5
19345
0.75%
7
14509
0.75%
11
9673
0.75%
47
2418
0.42%
96
1196
0.28%
1054
110.02
0.18%
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