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參數(shù)資料
| 型號： | CL-PS7111-VC-A |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Low-Power System-on-a-Chip |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP208 |
| 封裝： | VQFP-208 |
| 文件頁數(shù)： | 73/105頁 |
| 文件大?。?/td> | 1207K |
| 代理商： | CL-PS7111-VC-A |
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PRELIMINARY DATA BOOK v2.0
September 1997
72
REGISTER DESCRIPTIONS
CL-PS7111
Low-Power System-on-a-Chip
5.40
Interrupt Status Register 2 — INTSR2
This register is an extension of INTSR1, containing status bits for the features that are new to CL-PS7111.
The interrupt status register reflects the current state of the new interrupt sources within CL-PS7111.
Each bit is set if the appropriate interrupt is active.
5.41
Interrupt Mask Register 2 — INTMR2
This register is an extension of INTMR1, containing interrupt mask bits for the features which are new for
CL-PS7111. Refer to INTSR2 for individual bit details.
5.42
Keyboard End-of-Interrupt Location — KBDEOI
A write to this location clears the KBDINT keyboard interrupt.
15
14
13
12
11
10
9
8
Reserved
URXINT2
UTXINT2
Reserved
7
6
5
4
3
2
1
0
Reserved
KBDINT
Bit
Description
15:14
Reserved
13
URXINT2:
UART2 receive FIFO half-full interrupt. The function of this interrupt source depends on whether the UART2
FIFO is enabled. If the FIFO is disabled, this interrupt is active when there is valid Rx data in the UART2 Rx Data Hold-
ing register and is cleared by reading this data. If the FIFO is enabled, this interrupt is active when the UART2 Rx FIFO
is half or more full, or if the FIFO is non empty and no more characters are received for a 3-character time-out period.
It is cleared by reading all the data from the Rx FIFO.
12
UTXINT2:
UART2 transmit FIFO half-empty interrupt. The function of this interrupt source depends on whether the
UART2 FIFO is enabled. If the FIFO is disabled (FIFOEN bit is clear in the UART2 Bit Rate and Line Control register),
this interrupt is active when there is no data in the UART2 Tx Data Holding register, and is cleared by writing to the
UART2 Data register. If the FIFO is enabled, this interrupt is active when the UART2 Tx FIFO is half or more empty
and is cleared by filling the FIFO to at least half full.
11:1
Reserved
0
KBDINT:
Keyboard interrupt. This interrupt is generated whenever a key is pressed, from the logical OR of the first 6 or
all 8 of the Port A inputs (depending on the state of the KBD6 bit in the SYSCON2 register). The interrupt request is
latched and can be deasserted by writing to the KBDEOI location.
15
14
13
12
11
10
9
8
Reserved
URXINT2
UTXINT2
Reserved
7
6
5
4
3
2
1
0
Reserved
KBDINT
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