參數(shù)資料
型號(hào)： BX80551PG3000FN
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 3000 MHz, MICROPROCESSOR, PBGA775
封裝： FLIP CHIP, LGA-775
文件頁(yè)數(shù)： 72/106頁(yè)
文件大?。?/td> 2713K
代理商： BX80551PG3000FN
68
Datasheet
Land Listing and Signal Descriptions
D[63:0]#
Input/
Output
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path
between the processor FSB agents, and must connect the appropriate pins/
lands on all such agents. The data driver asserts DRDY# to indicate a valid data
transfer.
D[63:0]# are quad-pumped signals and will, thus, be driven four times in a
common clock period. D[63:0]# are latched off the falling edge of both
DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a
pair of one DSTBP# and one DSTBN#. The following table shows the grouping
of data signals to data strobes and DBI#.
Furthermore, the DBI# signals determine the polarity of the data signals. Each
group of 16 data signals corresponds to one DBI# signal. When the DBI# signal
is active, the corresponding data group is inverted and therefore sampled active
high.
DBI[3:0]#
Input/
Output
DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the
polarity of the D[63:0]# signals.The DBI[3:0]# signals are activated when the
data on the data bus is inverted. If more than half the data bits, within a 16-bit
group, would have been asserted electrically low, the bus agent may invert the
data bus signals for that particular sub-phase for that 16-bit group.
DBR#
Output
DBR# (Debug Reset) is used only in processor systems where no debug port is
implemented on the system board. DBR# is used by a debug port interposer so
that an in-target probe can drive system reset. If a debug port is implemented in
the system, DBR# is a no connect in the system. DBR# is not a processor
signal.
DBSY#
Input/
Output
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on
the processor FSB to indicate that the data bus is in use. The data bus is
released after DBSY# is de-asserted. This signal must connect the appropriate
pins/lands on all processor FSB agents.
DEFER#
Input
DEFER# is asserted by an agent to indicate that a transaction cannot be
ensured in-order completion. Assertion of DEFER# is normally the
responsibility of the addressed memory or input/output agent. This signal must
connect the appropriate pins/lands of all processor FSB agents.
DP[3:0]#
Input/
Output
DP[3:0]# (Data parity) provide parity protection for the D[63:0]# signals. They
are driven by the agent responsible for driving D[63:0]#, and must connect the
appropriate pins/lands of all processor FSB agents.
Table 4-3. Signal Description (Sheet 3 of 8)
Name
Type
Description
Quad-Pumped Signal Groups
Data Group
DSTBN#/
DSTBP#
DBI#
D[15:0]#
0
D[31:16]#
1
D[47:32]#
2
D[63:48]#
3
DBI[3:0] Assignment To Data Bus
Bus Signal
Data Bus Signals
DBI3#
D[63:48]#
DBI2#
D[47:32]#
DBI1#
D[31:16]#
DBI0#
D[15:0]#
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