參數(shù)資料
型號(hào)： BX80551PG3000FN
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 3000 MHz, MICROPROCESSOR, PBGA775
封裝： FLIP CHIP, LGA-775
文件頁(yè)數(shù)： 26/106頁(yè)
文件大?。?/td> 2713K
代理商： BX80551PG3000FN
26
Datasheet
Electrical Specifications
2.5.4
Die Voltage Validation
Overshoot events on the processor must meet the specifications in Table 2-6 when measured across
the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be
ignored. These measurements of processor die level overshoot must be taken with a bandwidth
limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit. Refer to the Voltage
Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for additional voltage
regulator validation details.
2.6
Signaling Specifications
Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling
technology. This technology provides improved noise margins and reduced ringing through low
voltage swings and controlled edge rates. Platforms implement a termination voltage level for
GTL+ signals defined as VTT. Because platforms implement separate power planes for each
processor (and chipset), separate VCC and VTT supplies are necessary. This configuration allows
for improved noise tolerance as processor frequency increases. Speed enhancements to data and
address busses have caused signal integrity considerations and platform design methods to become
even more critical than with previous processor families.
The GTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine
if a signal is a logical 0 or a logical 1. GTLREF must be generated on the motherboard (see
Table 2-16 for GTLREF specifications). Termination resistors (RTT) for GTL+ signals are provided
on the processor silicon and are terminated to VTT. Intel chipsets will also provide on-die
termination, thus eliminating the need to terminate the bus on the motherboard for most GTL+
signals.
2.6.1
FSB Signal Groups
The FSB signals have been combined into groups by buffer type. GTL+ input signals have
differential input buffers that use GTLREF as a reference level. In this document, the term "GTL+
Input" refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly,
"GTL+ Output" refers to the GTL+ output group as well as the GTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock signals whose timings are specified with respect to
rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source
synchronous signals that are relative to their respective strobe lines (data and address) as well as
rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can
become active at any time during the clock cycle. Table 2-7 identifies which signals are common
clock, source synchronous and asynchronous.
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