參數(shù)資料
型號: BX80551PG3000FN
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 3000 MHz, MICROPROCESSOR, PBGA775
封裝: FLIP CHIP, LGA-775
文件頁數(shù): 31/106頁
文件大?。?/td> 2713K
代理商: BX80551PG3000FN
30
Datasheet
Electrical Specifications
Table 2-12. PWRGOOD Input and TAP Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes1, 2
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
All outputs are open drain.
V
HYS
Input Hysteresis
200
350
mV
3
3.
VHYS represents the amount of hysteresis, nominally centered about 0.5 * VTT, for all TAP inputs.
V
T+
Input low to high
threshold voltage
0.5 * (V
TT + V
HYS_MIN)
0.5 * (V
TT + V
HYS_MAX)V
4
4.
The VTT referred to in these specifications refers to instantaneous VTT.
V
T-
Input high to low
threshold voltage
0.5 * (V
TT – V
HYS_MAX)
0.5 * (V
TT – V
HYS_MIN)V
V
OH
Output High Voltage
N/A
V
TT
V
I
OL
Output Low Current
-
45
mA
5
5.
The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test
load.
I
LI
Input Leakage Current
-
± 200
A
6
6.
Leakage to VSS with land held at VTT.
I
LO
Output Leakage
Current
-± 200
A
R
ON
Buffer On Resistance
7
12
Ω
Table 2-13. GTL+ Asynchronous Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes1
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
V
IL
Input Low Voltage
0.0
VTT/2 – (0.10 * VTT)-
2, 3
2.
VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3.
LINT0/INTR, LINT1/NMI, and FORCEPR# use GTLREF as a reference voltage. For these two signals,
VIH = GTLREF + (0.10 * VTT) and VIL= GTLREF – (0.10 * VTT).
V
IH
Input High Voltage
VTT/2 + (0.10 * VTT)VTT
-
3, 4, 5, 6
4.
VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5.
VIH and VOH may experience excursions above VTT.
6.
The VTT referred to in these specifications refers to instantaneous VTT.
V
OH
Output High Voltage
0.90*VTT
VTT
V
5, 6, 7
7.
All outputs are open drain.
I
OL
Output Low Current
VTT/[(0.50*RTT_MIN) +
RON_MIN]
A
8
8.
The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test
load.
I
LI
Input Leakage Current
N/A
± 200
A
9
9.
Leakage to VSS with land held at VTT.
I
LO
Output Leakage
Current
N/A
± 200
A
10
10.
Leakage to VTT with land held at 300 mV.
R
ON
Buffer On Resistance
8
12
Ω
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