參數(shù)資料
型號(hào)： BX80551PG3000FN
廠(chǎng)商： INTEL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 3000 MHz, MICROPROCESSOR, PBGA775
封裝： FLIP CHIP, LGA-775
文件頁(yè)數(shù)： 28/106頁(yè)
文件大小： 2713K
代理商： BX80551PG3000FN
28
Datasheet
Electrical Specifications
2.6.2
GTL+ Asynchronous Signals
The signals A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize CMOS input buffers. GTL+
asynchronous signals follow the same DC requirements as GTL+ signals; however, the outputs are
not actively driven high (during a logical 0 to 1 transition) by the processor. GTL+ asynchronous
signals do not have setup or hold time specifications in relation to BCLK[1:0].
All of the GTL+ Asynchronous signals are required to be asserted/deasserted for at least six
BCLKs in order for the processor to recognize the proper signal state. See Section 2.6.3 for the DC
specifications for the GTL+ Asynchronous signal groups. See Table 6.2 for additional timing
requirements for entering and leaving the low power states.
Table 2-8. Signal Characteristics
Signals with R
TT
Signals with no R
TT
A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,
BNR#, BOOTSELECT1, BPRI#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#,
DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#, HIT#,
HITM#, IMPSEL1, LOCK#, MCERR#,
PROCHOT#, REQ[4:0]#, RS[2:0]#, RSP#,
TRDY#, MSID[1:0]1
NOTES:
1.
These signals have a 250–5000
Ω pullup to V
TT rather than on-die termination.
A20M#, BCLK[1:0], BPM[5:0]#, BR0#, BSEL[2:0],
COMP[3:0], FERR#/PBE#, IERR#, IGNNE#, INIT#,
LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#,
SKTOCC#, SMI#, STPCLK#, TDO, TESTHI[13:0],
THERMDA, THERMDC, THERMTRIP#, VID[5:0],
VTTPWRGD, GTLREF[1:0], TCK, TDI, TRST#, TMS
Open Drain Signals2
2.
Signals that do not have R
TT, nor are actively driven to their high-voltage level.
BSEL[2:0], VID[5:0], THERMTRIP#, FERR#/
PBE#, IERR#, BPM[5:0]#, BR0#, TDO, VTT_SEL,
LL_ID[1:0]
Table 2-9. Signal Reference Voltages
GTLREF
VTT/2
BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#,
BINIT#, BNR#, HIT#, HITM#, MCERR#, PROCHOT#,
BR0#, A[35:0]#, ADS#, ADSTB[1:0]#, AP[1:0]#,
BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#,
LOCK#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#
BOOTSELECT, VTTPWRGD, A20M#, IGNNE#,
INIT#, PWRGOOD1, SMI#, STPCLK#, TCK1, TDI1,
TMS1, TRST#1, MSID[1:0]
NOTES:
1.
These signals also have hysteresis added to the reference voltage. See Table 2-12 for more information.
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