參數(shù)資料
型號： AD9925BBCZRL
廠商： ANALOG DEVICES INC
元件分類： 消費家電
英文描述： CCD Signal Processor with Vertical Driver and Precision Timing Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA96
封裝： 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96
文件頁數(shù)： 79/96頁
文件大?。?/td> 1447K
代理商： AD9925BBCZRL
AD9925
Table 64. Vertical Sequence 6 (VSEQ6) Register Map
Address Data Bit Content Default Value Register Name
B0
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[12]
[23:12]
B1
[11:0]
[23:12]
X
B2
[11:0]
[23:12]
X
B3
[11:0]
[23:12]
X
B4
[11:0]
[23:12]
X
B5
[11:0]
[23:12]
X
B6
[11:0]
[23:12]
X
B7
[11:0]
[23:12]
X
Rev. A | Page 79 of 96
Register Description
Masking Polarity during HBLK. H1 [0], H3 [1].
CLPOB Start Polarity.
PBLK Start Polarity.
Selected Vertical Pattern Group for Vertical Sequence 6.
Enable Masking of Vertical outputs (specified by FREEZE/RESUME
registers).
Enable HBLK Alternation.
13
th
Bit for HD Length Counter Allows HD Length up to 8191 Pixels.
Unused.
Number of Selected Vertical Pattern Group Repetitions for Odd Lines.
Number of Selected Vertical Pattern Group Repetitions for Even Lines.
Start Position in the Line for the Selected Vertical Pattern Group.
HD Line Length (Number of Pixels) for Vertical Sequence 6.
PBLK Toggle Position 1 for Vertical Sequence 6.
PBLK Toggle Position 2 for Vertical Sequence 6.
HBLK Toggle Position 1 for Vertical Sequence 6.
HBLK Toggle Position 2 for Vertical Sequence 6.
HBLK Toggle Position 3 for Vertical Sequence 6.
HBLK Toggle Position 4 for Vertical Sequence 6.
HBLK Toggle Position 5 for Vertical Sequence 6.
HBLK Toggle Position 6 for Vertical Sequence 6.
CLPOB Toggle Position 1 for Vertical Sequence 6.
CLPOB Toggle Position 2 for Vertical Sequence 6.
X
X
X
X
X
X
X
HBLKMASK_6
CLPOBPOL_6
PBLKPOL_6
VPATSEL_6
VMASK_6
HBLKALT_6
HDLEN13_6
UNUSED
VPATREPO_6 V
PATREPE_6
VPATSTART_6
HDLEN_6
PBLKTOG1_6
PBLKTOG2_6
HBLKTOG1_6
HBLKTOG2_6
HBLKTOG3_6
HBLKTOG4_6
HBLKTOG5_6
HBLKTOG6_6
CLPOBTOG1_6
CLPOBTOG2_6
X
X
X
X
X
X
X
Table 65. Vertical Sequence 7 (VSEQ7) Register Map
Address Data Bit Content Default Value Register Name
B8
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[12]
[23:12]
B9
[11:0]
[23:12]
X
BA
[11:0]
[23:12]
X
BB
[11:0]
[23:12]
X
BC
[11:0]
[23:12]
X
BD
[11:0]
[23:12]
X
BE
[11:0]
[23:12]
X
BF
[11:0]
[23:12]
X
Register Description
Masking Polarity during HBLK. H1 [0], H3 [1].
CLPOB Start Polarity.
PBLK Start Polarity.
Selected Vertical Pattern Group for Vertical Sequence 7.
Enable Masking of Vertical Outputs (Specified by FREEZE/RESUME Registers).
Enable HBLK Alternation.
13
th
Bit for HD Length Counter Allows HD Length up to 8191 Pixels.
Unused.
Number of Selected Vertical Pattern Group Repetitions for Odd Lines.
Number of Selected Vertical Pattern Group Repetitions for Even Lines.
Start Position in the Line for the Selected Vertical Pattern Group.
HD Line Length (Number of Pixels) for Vertical Sequence 7.
PBLK Toggle Position 1 for Vertical Sequence 7.
PBLK Toggle Position 2 for Vertical Sequence 7.
HBLK Toggle Position 1 for Vertical Sequence 7.
HBLK Toggle Position 2 for Vertical Sequence 7.
HBLK Toggle Position 3 for Vertical Sequence 7.
HBLK Toggle Position 4 for Vertical Sequence 7.
HBLK Toggle Position 5 for Vertical Sequence 7.
HBLK Toggle Position 6 for Vertical Sequence 7.
CLPOB Toggle Position 1 for Vertical Sequence 7.
CLPOB Toggle Position 2 for Vertical Sequence 7.
X
X
X
X
X
X
X
HBLKMASK_7
CLPOBPOL_7
PBLKPOL_7
VPATSEL_7
VMASK_7
HBLKALT_7
HDLEN13_7
UNUSED
VPATREPO_7
VPATREPE_7
VPATSTART_7
HDLEN_7
PBLKTOG1_7
PBLKTOG2_7
HBLKTOG1_7
HBLKTOG2_7
HBLKTOG3_7
HBLKTOG4_7
HBLKTOG5_7
HBLKTOG6_7
CLPOBTOG1_7
CLPOBTOG2_7
X
X
X
X
X
X
X
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