- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373970 > AD9925BBCZRL (ANALOG DEVICES INC) CCD Signal Processor with Vertical Driver and Precision Timing Generator PDF資料下載
參數(shù)資料
| 型號： | AD9925BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA96 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96 |
| 文件頁數(shù)： | 27/96頁 |
| 文件大小： | 1447K |
| 代理商： | AD9925BBCZRL |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當(dāng)前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁
AD9925
Vertical Sequences (VSEQ)
The vertical sequences are created by selecting one of the 10 ver-
cal pattern groups and adding repeats, the start position, and
horizontal clamping and blanking information. Up to 10 verti-
cal sequences may be programmed, each using the registers
shown in Table 14. Figure 36 shows how the different registers
are used to generate each vertical sequence.
Rev. A | Page 27 of 96
The VPATSEL register selects which vertical pattern group will
be used in a given vertical sequence. The basic vertical pattern
group can have repetitions added for high speed line shifts or
line binning by using the VPATREPO and VPATREPE registers.
Generally, the same number of repetitions is programmed into
both registers, but if a different number of repetitions is re-
quired on odd and even lines, separate values may be used for
each register (see the Generating Line Alternation for Vertical
Sequence and HBLK section). The VPATSTART register speci-
fies the pixel location where the vertical pattern group will start.
The VMASK register is used in conjunction with the FREEZE/
RESUME registers to enable optional masking of the vertical
outputs. Either or both of the FREEZE1/RESUME1 and
FREEZE2/RESUME2 registers can be enabled using the
VMASK register.
Table 14. Vertical Sequence Registers (See Table 10 and Table 11 for the HBLK, CLPOB, and PBLK registers)
Register
Length Range
VPATSEL
4 b
0 to 9 Vertical Pattern Group No.
VMASK
2 b
0 to 3 Mask Mode
(in pixels) is programmable using the HDLEN
registers. Each vertical sequence can have a different line length
to accommodate the various image readout techniques. The
maximum number of pixels per line is 8192. Note that the 13
th
bit
(MSB) of the line length is located in a separate register. Also
note that the last line of the field is separately programmable
using the HDLAST register, located in the field register section.
Additional vertical sequences are provided in Register Bank 3
for the XV7 and XV8 outputs. This allows the AD9925 to re-
main backward-compatible with the AD9995 register settings
while still providing additional flexibility with XV7 and XV8 for
new CCDs.
As described in the Hold Area Using FREEZE/RESUME Regis-
ters section, the hold registers in Bank 3 are used to specify a
hold area instead of vertical masking. The FREEZE/RESUME
registers are used to define the hold area. The XV78HOLDEN
registers are used to specify whether XV7 and XV8 will use the
hold area or not.
Description
Selected Vertical Pattern Group for Each Vertical Sequence.
Enables the Masking of V1 to V6 Outputs at the Locations Specified by the
FREEZE/RESUME Registers.
0 = No Mask.
1 = Enable Freeze1/Resume1.
2 = Enable Freeze2/Resume2.
3 = Enable Both 1 and 2.
Number of Repetitions for the Vertical Pattern Group for Odd Lines. If no
odd/even alternation is required, set equal to VPATREPE.
Number of Repetitions for the Vertical Pattern Group for Even Lines. If no
odd/even alternation is required, set equal to VPATREPO.
Start Position for the Selected Vertical Pattern Group.
HD Line Length for Lines in Each Vertical Sequence. Note that 13
th
bit (MSB)
of the line length is located in a separate register to maintain compatibility
with AD9995.
ti
The line length
VPATREPO
12 b
0 to 4095 Number of Repeats
VPATREPE
12 b
0 to 4095 Number of Repeats
VPATSTART
HDLEN
12 b
13 b
0 to 4095 Pixel Location
0 to 8191 Number of Pixels
HOLD
1
1 b
High/Low
Enable Hold Area Instead of Vertical Masking, Using FREEZE/RESUME
Registers.
XV78HOLDEN
1
1 b
High/Low
Enable XV7 and XV8 to Use Hold Area.
0 = Disable.
1 = Enable.
1
Located in Bank 3, vertical sequence registers for XV7 and XV8.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9925 | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| AD9925BBCZ | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| AD9927 | 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
| AD9927BBCZ | 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
| AD9927BBCZRL | 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9925KBCZ | 制造商:Analog Devices 功能描述:12 BIT, 36 MSPS CCD SIGNAL PROCESSOR W/VERTICAL DRIVER - Bulk |
| AD9926BBCZ | 制造商:Analog Devices 功能描述: |
| AD9926BBCZRL | 制造商:Analog Devices 功能描述: |
| AD9927 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
| AD9927BBCZ | 制造商:Analog Devices 功能描述:AFE Video 1ADC 14-Bit 1.8V/3V 128-Pin CSP-BGA 制造商:Analog Devices 功能描述:IC 14BIT CCD SIGNAL PROCESSOR SMD |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。