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參數(shù)資料
| 型號： | AD9925BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA96 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96 |
| 文件頁數(shù)： | 16/96頁 |
| 文件大?。?/td> | 1447K |
| 代理商： | AD9925BBCZRL |
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AD9925
Rev. A | Page 16 of 96
7. H3 RISING EDGE POSITION AND 8: H3 FALLING EDGE POSITION (H4 I
H1
H2
RG
H3
CCD
SIGNAL
PROGRAMMABLE CLOCK POSITIONS:
1. RG RISING EDGE.
2. RG FALLING EDGE.
3. SHP SAMPLE LOCATION.
4. SHD SAMPLE LOCATION.
5. H1 RISING EDGE POSITION AND 6: H1 FALLING EDGE POSITION (H2 IS INVERSE OF H1).
H4
3
2
S INVERSE OF H3).
4
1
5
6
7
8
0
Figure 18. High Speed Clock Programmable Locations
ws the de
ck signals.
RG Out
ng locatio
of the high
rogra mable timing posi
tpu
vers for the RG
ers are p
erful enough to
CD inputs. The H-driver and RG current can be adjusted for
ptimum rise/fall time with a particular load by using the
RVCONTROL register (Addr x35). The 3-bit drive setting for
each output is adjustable in 4.1 mA increments, with the mini-
mum setting of 0 equal to OFF or three-state and the
etting of 7 equal to 30.1 mA.
s
20, the H2 and H4
2
ossover voltage is approximately
ssover voltage is not programm
cro
e output swing. The
50% of th
able.
ta Outputs
x37, Bits [5:0]). Any
s shown in Figure 21.
in phase,
ut-
put phase can also be held fixed with respect to the data outputs
by changing the DCLKMODE register high (Addr x37, Bit [6]).
In this mode, the DCLK output will remain at a fixed phase
equal to CLO (the inverse of CLI), while the data output phase
is still programmable.
There is a fixed output delay from the DCLK rising edge to the
DOUT transition, called t
OD
. This delay can be programmed to
four values between 0 ns and 12 ns by using the DOUTDELAY
Bits [8:7]). T
register (Addr x37,
.
peline delay through the
he CCD input is sampled
ntil the data is available.
delay u
Figure 22.
11 cycle
Table 8. Timing Core Register Parameters for H1, H3, RG, SHP/SHD
arameter
Length
P
Polarity
1 b
Positive Edge
6 b
Negative Edge
6 b
Sampling Location
6 b
Drive Strength
3 b
Range
High/Low
0 to 47 Edge Location
0 to 47 Edge Location
0 to 47 Edge Location
0 to 47 Current Steps
Description
Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion)
Positive Edge Location for H1, H3, and RG
Negative Edge Location for H1, H3, and RG
Sampling Location for Internal SHP and SHD Signals
Drive Current for H1 to H4 and RG Outputs (4.1 mA per Step)
Figure 20 sho
speed clo
H-Driver and
In addition to the p
features on-chip o
puts. These driv
C
o
D
fault timi
ns for all
puts
t dri
ow
u
tions, the AD9925
and H1 to H4 out-
directly drive the
maximum
As shown in Figure 18, Figure 19, and Figure
inverses of H1 and H3,
outputs are
cr
respectively. The H1/H
Digital Da
The AD9925 data output and DCLK phase are programmable
using the DOUTPHASE register (Addr
edge from 0 to 47 may be programmed, a
Normally, the DOUT and DCLK signals will track
based on the DOUTPHASE register contents. The DCLK o
he default value is 8 ns
The pi
After t
AD9925 is shown in
by SHD, there is an
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