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參數(shù)資料
| 型號： | AD9925BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA96 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96 |
| 文件頁數(shù)： | 18/96頁 |
| 文件大?。?/td> | 1447K |
| 代理商： | AD9925BBCZRL |
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AD9925
Rev. A | Page 18 of 96
P[48] = P[0]
P[24]
P[36]
NOTES
1. DATA OUTPUT (DOUT) AND DCLK PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
2. WITHIN 1 CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS.
3. OUTPUT DELAY (
t
OD
) FROM DCLK RISING EDGE TO DOUT RISING EDGE IS PROGRAMMABLE.
P[0]
P[12]
PIXEL
PERIOD
DOUT
DCLK
t
OD
0
Figure 21. Digi
tal Output Phase Adjustment
E = 0.
FT DOUT TRA
HICH IS EQ
FOR THE DOUTPHASE LOCATION.
SHPLOC EDGE OR THE 11 EDGES FOLLOWING SHPLOC.
ECOMMENDED VALUE FOR
t
(DOUT DLY) IS 4ns.
6. THE DOUT LATCH CAN BE BYPASSED U
DOUT PINS. THIS CONFIGURATION IS R
SING REGISTER 0x03, BIT [4] = 1, SO THAT THE ADC DATA OUTPUTS APPEAR DIRECTLY AT THE
ECOMMENDED IF ADJUSTABLE DOUT PHASE IS NOT REQUIRED.
0
NOTES
1. TIMING VALUES SHOWN ARE SHDLOC = 0, WITH DCLKMOD
2. HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHI
3. INHIBIT TIME FOR DOUT PHASE IS DEFINED BY t
, W
11 EDGE LOCATIONS FOLLOWING SHDLOC NOT BE USED
4. RECOMMENDED VALUE FOR DOUT PHASE IS TO USE THE
5. R
NSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.
UAL TO SHDLOC PLUS 11 EDGES. IT IS RECOMMENDED THAT THE
DCLK
DOUT
N – 13
N – 8
N – 9
N – 10
N – 11
N – 12
CCDIN
SHD
(INTERNAL)
N
N + 1
N + 2
N + 4
N + 3
CLI
N + 12
N + 11
N + 10
N + 9
N + 8
N + 7
6
N + 13
N +
N + 5
N
N – 7
N – 3
N – 4
N – 5
– 6
N – 2
N – 1
N + 1
N
SAMPLE PIXEL N
t
N – 1
PIPELINE LATENC
t
DOUTINH
Y = 11 CYCLES
N + 2
N – 13
N – 8
N – 9
N – 10
N – 11
N – 12
N – 3
N – 4
N – 5
N – 2
N – 1
N + 1
N
N + 2
N – 6
N – 7
ADC DOUT
(INTERNAL)
Figure
utput Pipeline Delay
ONTAL
P
ho
tal cl
lses
programmable to suit a variety of applications. Individu
trol is provided for CLPOB, PBLK, and HBLK during th
d. Th
and blanking patterns to be changed at each stage of the
out, which accommodates the different image transfer t
and high speed line shifts.
Individual CLPOB and PBLK Patterns
he AFE horizontal timing consists of CLPOB and PBLK, as
wn in Figure 23. These two signals are independently pro-
rammed using the registers in Table 10. SPOL is the start po-
larity for the signal, and TOG1 and TOG2 are the first and sec-
ond toggle positions of the pulse. Both signals ar
and should be programmed accordingly.
e dark pixel clam
te vertical sequences
be changed accordingly with
each change in the vertical timing.
CLPOB Masking Area
Additionally, the AD9925 allows the CLPOB signal to be dis-
abled during certain lines in the field without changing any of
B pattern settings. There are two ways to use
CLPOB masking. First, the six CLPOBMASK registers can be used
22. Digital Data O
HORIZ
The AD9925’s
CLAM ING AND BLANKING
rizon
amping and blanking pu
are fully
al con-
e differ-
ping
read-
iming
A separate pattern for CLPOB and PBLK may be programmed
for every 10 vertical sequences. As described in the Vertical
Timing Generation section, up to 10 separa
can be created, each containing a unique pulse pattern for
CLPOB and PBLK. Figure 37 shows how the sequence change
positions divide the readout field into different regions. A dif-
ferent vertical sequence can be assigned to each region, allowing
the CLPOB and PBLK signals to
ent regions of each fiel
is allows th
T
sho
g
e active low
the existing CLPO
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